Home Microcontrollers (MCUs) & processors Digital signal processors (DSPs)
Home
Microcontrollers (MCUs) & processors
Digital signal processors (DSPs)

SMJ320C6701-SP

ACTIVE

Space grade C6701 floating-point DSP - rad-tolerant class V with ceramic package

Order now
Data sheet

SMJ320C6701-SP

ACTIVE
Data sheet Order now

Product details

DSP type 1 C67x DSP (max) (MHz) 140 CPU 32-/64-bit Operating system DSP/BIOS Rating Space Operating temperature range (°C) -55 to 125
DSP type 1 C67x DSP (max) (MHz) 140 CPU 32-/64-bit Operating system DSP/BIOS Rating Space Operating temperature range (°C) -55 to 125
CFCBGA (GLP) 429 729 mm² 27 x 27 FCLGA (ZMB) 429 729 mm² 27 x 27
  • Rad-Tolerant: 100-kRad (Si) TID
  • SEL Immune at 89MeV-cm2/mg LET Ions
  • QML-V Qualified, SMD 5962-98661
  • Highest-Performance Floating-Point Digital
    Signal Processor (DSP) SMJ320C6701
    • 7-ns Instruction Cycle Time
    • 140-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • Up to One GFLOPS Performance
    • Pin Compatible With ’C6201 Fixed-Point DSP
  • SMJ: QML Processing to MIL-PRF-38535
  • SM: Standard Processing
  • Operating Temperature Ranges
    • –55°C to 115°C
    • –55°C to 125°C
  • VelociTI Advanced Very Long Instruction
    Word (VLIW) ’C67x CPU Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating and Fixed Point)
      • Two ALUs (Fixed Point)
      • Two Multipliers (Floating and Fixed Point)
    • Load-Store Architecture With 32
      32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision
      Instructions
    • Hardware Support for IEEE Double-Precision
      Instructions
    • Byte Addressable (8-/16-/32-Bit Data)
    • 32-Bit Address Range
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit Counting
    • Normalization
  • 1M-Bit On-Chip SRAM
    • 512K-Bit Internal Program/Cache
      (16K 32-Bit Instructions)
    • 512K-Bit Dual-Access Internal Data
      (64K Bytes)
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Synchronous Memories:
      SDRAM and SBSRAM
    • Glueless Interface to Asynchronous Memories:
      SRAM and EPROM
  • Four-Channel Bootloading
    Direct Memory Access (DMA) Controller
    With Auxiliary Channel
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST Bus Switching Compatible
    • Up to 256 Channels Each
    • AC97 Compatible
    • Serial Peripheral Interface (SPI)
      Compatible (Motorola)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked Loop (PLL) Clock Generator
  • IEEE Std 1149.1 (JTAG(1))
    Boundary Scan Compatible
  • 429-Pin Ceramic Ball Grid Array (CBGA/GLP) and
    Ceramic Land Grid Array (CLGA/ZMB) Package Types
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.9 V Internal
  • Engineering Evaluation (/EM) Samples are Available(2)

(1) IEEE Std 1149.1-1990 Test Access Port and Boundary Scan Architecture
(2) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life.
  • Rad-Tolerant: 100-kRad (Si) TID
  • SEL Immune at 89MeV-cm2/mg LET Ions
  • QML-V Qualified, SMD 5962-98661
  • Highest-Performance Floating-Point Digital
    Signal Processor (DSP) SMJ320C6701
    • 7-ns Instruction Cycle Time
    • 140-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • Up to One GFLOPS Performance
    • Pin Compatible With ’C6201 Fixed-Point DSP
  • SMJ: QML Processing to MIL-PRF-38535
  • SM: Standard Processing
  • Operating Temperature Ranges
    • –55°C to 115°C
    • –55°C to 125°C
  • VelociTI Advanced Very Long Instruction
    Word (VLIW) ’C67x CPU Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating and Fixed Point)
      • Two ALUs (Fixed Point)
      • Two Multipliers (Floating and Fixed Point)
    • Load-Store Architecture With 32
      32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision
      Instructions
    • Hardware Support for IEEE Double-Precision
      Instructions
    • Byte Addressable (8-/16-/32-Bit Data)
    • 32-Bit Address Range
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit Counting
    • Normalization
  • 1M-Bit On-Chip SRAM
    • 512K-Bit Internal Program/Cache
      (16K 32-Bit Instructions)
    • 512K-Bit Dual-Access Internal Data
      (64K Bytes)
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Synchronous Memories:
      SDRAM and SBSRAM
    • Glueless Interface to Asynchronous Memories:
      SRAM and EPROM
  • Four-Channel Bootloading
    Direct Memory Access (DMA) Controller
    With Auxiliary Channel
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST Bus Switching Compatible
    • Up to 256 Channels Each
    • AC97 Compatible
    • Serial Peripheral Interface (SPI)
      Compatible (Motorola)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked Loop (PLL) Clock Generator
  • IEEE Std 1149.1 (JTAG(1))
    Boundary Scan Compatible
  • 429-Pin Ceramic Ball Grid Array (CBGA/GLP) and
    Ceramic Land Grid Array (CLGA/ZMB) Package Types
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.9 V Internal
  • Engineering Evaluation (/EM) Samples are Available(2)

(1) IEEE Std 1149.1-1990 Test Access Port and Boundary Scan Architecture
(2) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life.

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 140 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The ’C6701 has a complete set of development tools that includes a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 140 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The ’C6701 has a complete set of development tools that includes a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
filter Find other Digital signal processors (DSPs)
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 10
Type Title Date
* Data sheet Rad-Tolerant Class-V Floating-Point Digital Signal Processor datasheet (Rev. F) 26 Sep 2013
* SMD SMJ320C6701-SP SMD 5962-98661 08 Jul 2016
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 31 Aug 2023
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 17 Nov 2022
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 Oct 2022
Selection guide TI Space Products (Rev. I) 03 Mar 2022
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
More literature QML Class V Product Portfolio 02 Sep 2004
More literature SMJ320C6701/5962-9866101QXA (Rev. M) 03 May 2002
More literature Military C6000 DSPs (Rev. A) 08 May 2000

Design & development

Please view the Design & development section on a desktop.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos