Home Logic & voltage translation Flip-flops, latches & registers Counters
Home
Logic & voltage translation
Flip-flops, latches & registers
Counters

CD54HC4017

ACTIVE

High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

Order now
Data sheet

CD54HC4017

ACTIVE
Data sheet Order now

Product details

Function Counter Bits (#) 10 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Function Counter Bits (#) 10 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • 2-V to 6-V Operation
  • Fully Static Operation
  • Buffered Inputs
  • Common Reset
  • Positive-Edge Clocking
  • Balanced Propagation Delay and Transition Times
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)
  • 2-V to 6-V Operation
  • Fully Static Operation
  • Buffered Inputs
  • Common Reset
  • Positive-Edge Clocking
  • Balanced Propagation Delay and Transition Times
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE\) input to cascade several stages. CE\ disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.

The CD54HC4017 is characterized for operation over the full military temperature range of -55°C to 125°C.

The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE\) input to cascade several stages. CE\ disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.

The CD54HC4017 is characterized for operation over the full military temperature range of -55°C to 125°C.
filter Find other Counters
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 15
Type Title Date
* Data sheet Decade Counter/Divider With Ten Decoded Outputs datasheet 19 Mar 1999
* SMD CD54HC4017 SMD 8601101EA 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Package Pins CAD symbols, footprints & 3D models
CDIP (J) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos