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Inverting buffers & drivers

SN54HC240

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Military 8-ch, 2-V to 6-V inverters with 3-state outputs

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Data sheet

SN54HC240

ACTIVE
Data sheet Order now

Product details

Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 8 IOL (max) (mA) 6 IOH (max) (mA) -6 Supply current (max) (µA) 80 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns) Rating Military Operating temperature range (°C) -55 to 125
Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 8 IOL (max) (mA) 6 IOH (max) (mA) -6 Supply current (max) (µA) 80 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns) Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 20 167.464 mm² 24.2 x 6.92 CFP (W) 20 90.5828 mm² 13.09 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Wide operating voltage range of 2V to 6V
  • High-current outputs drive up to 15 LSTTL loads
  • Low power consumption, 80µA max ICC
  • Typical tpd = 9ns
  • ±6mA output drive at 5V
  • Low input current of 1µA max
  • 3-state outputs drive bus lines or buffer memory address registers
  • Wide operating voltage range of 2V to 6V
  • High-current outputs drive up to 15 LSTTL loads
  • Low power consumption, 80µA max ICC
  • Typical tpd = 9ns
  • ±6mA output drive at 5V
  • Low input current of 1µA max
  • 3-state outputs drive bus lines or buffer memory address registers

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
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Technical documentation

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Type Title Date
* Data sheet SNx4HC240 Octal Buffers and Line Drivers With 3-State Outputs datasheet (Rev. H) PDF | HTML 22 Aug 2024
* SMD SN54HC240 SMD 84074012A 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Package Pins CAD symbols, footprints & 3D models
CDIP (J) 20 Ultra Librarian
CFP (W) 20 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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