Table 11-1 Power Supply Rails on the 66AK2Hxx

11.2.1 Power-Up Sequencing

This section defines the requirements for a power-up sequencing from a power-on reset condition. There are two acceptable power sequences for the device.

The first sequence stipulates the core voltages starting before the IO voltages as shown below.

1. CVDD
2. CVDD1, CVDDT1, VDDAHV, AVDDAx, DVDD18
3. DVDD15
4. VDDALV, VDDUSB, VP, VPTX
5. DVDD33

The second sequence provides compatibility with other TI processors with the IO voltage starting before the core voltages as shown below.

1. VDDAHV, AVDDAx, DVDD18
2. CVDD
3. CVDD1, CVDDT1
4. DVDD15
5. VDDALV, VDDUSB, VP, VPTX
6. DVDD33

The clock input buffers for SYSCLK, ARMCLK, ALTCORECLK, DDR3ACLK, DDR3BCLK, PASSCLK, and SRIOSGMIICLK use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the device. Once CVDD is valid, it is acceptable that the P and N legs of these clocks may be held in a static state (either high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation, the clock inputs should be removed from the high impedance state shortly after CVDD is present.

If a clock input is not used, it must be held in a static state. To accomplish this, the N leg should be pulled to ground through a 1-kΩ resistor. The P leg should be tied to CVDD to ensure it will not have any voltage present until CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could cause damage to the device.

The device initialization is divided into two phases. The first phase consists of the time period from the activation of the first power supply until the point at which all supplies are active and at a valid voltage level. Either of the sequencing scenarios described above can be implemented during this phase. The figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire power stabilization phase.

This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL triggers the end of the initialization phase, but both must be inactive for the initialization to complete. POR must always go inactive before RESETFULL goes inactive as described below. SYSCLK1 in the following section refers to the clock that is used by the CorePacs. See Figure 11-7 for more details.

11.2.1.1 Core-Before-IO Power Sequencing

The details of the Core-before-IO power sequencing are defined in Table 11-2. Figure 11-1 shows power sequencing and reset control of the 66AK2Hxx. POR may be removed after the power has been stable for the required 100 µsec. RESETFULL must be held low for a period (see item 9 in Figure 11-1) after the rising edge of POR, but may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified. SYSCLK1 must always be active before POR can be removed.

NOTE

TI recommends a maximum of 80 ms between one power rail being valid and the next power rail in the sequence starting to ramp.

Table 11-2 Core-Before-IO Power Sequencing

ITEM	SYSTEM STATE
1	Begin Power Stabilization Phase CVDD (core AVS) ramps up. POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous reset (created from POR) is put into the reset state. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2a	CVDD1 and CVDDT1 (core constant) ramps at the same time or within 80 ms of CVDD. Although ramping CVDD1 simultaneously with CVDD is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage. The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. The timing for CVDD1 is based on CVDD valid. CVDD1 and DVDD18/ADDAVH/AVDDAx may be enabled at the same time but do not need to ramp simultaneously. CVDD1 may be valid before or after DVDD18/ADDAVH/AVDDAx are valid, as long as the timing above is met.
2b	VDDAHV, AVDDAx and DVDD18 ramp at the same time or shortly following CVDD. DVDD18 must be enabled within 80 ms of CVDD valid and must ramp monotonically and reach a stable level in 20ms or less. This results in no more than 100 ms from the time when CVDD is valid to the time when DVDD18 is valid. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. The timing for DVDD18/ADDAVH/AVDDAx is based on CVDD valid. DVDD18/ADDAVH/AVDDAx and CVDD1and CVDDT1 may be enabled at the same time but do not need to ramp simultaneously. DVDD18/ADDAVH/AVDDAx may be valid before or after CVDD1 and CVDDT1 are valid, as long as the timing above is met.
2c	Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low.
2d	The DDR3ACLK, DDR3BCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by item 7.
3	DVDD15 can ramp up within 80ms of when DVDD18 is valid. RESETSTAT is driven low once the DVDD18 supply is available. All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
3a	RESET may be driven high any time after DVDD18 is at a valid level. RESET must be high before POR is driven high.
4	VDDALV, VDDUSB, VP and VPTX ramp up within 80ms of when DVDD15 is valid. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
5	DVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSB, VP and VPTX are valid. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
6	POR must continue to remain low for at least 100 μs after all power rails have stabilized. End power stabilization phase
7	Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
8	RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
9	The rising edge of the RESETFULL will remove the reset to the eFuse farm allowing the scan to begin. Once device initialization and the eFuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles. End device initialization phase
10	GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
11	GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.

Figure 11-1 Core-Before-IO Power Sequencing

11.2.1.2 IO-Before-Core Power Sequencing

The timing diagram for IO-before-core power sequencing is shown in Figure 11-2 and defined in Table 11-3.

NOTE

TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp.

Table 11-3 IO-Before-Core Power Sequencing

ITEM	SYSTEM STATE
1	Begin Power Stabilization Phase VDDAHV, AVDDAx and DVDD18 ramp up. POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous reset (created from POR ) is put into the reset state. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2	CVDD (core AVS) ramps within 80 ms from the time ADDAHV, AVDDAx and DVDD18 are valid. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2a	RESET may be driven high any time after DVDD18 is at a valid level. must be high before POR is driven high.
3	CVDD1 and CVDDT1 (core constant) ramp at the same time or within 80 ms following CVDD. Although ramping CVDD1and CVDDT1 simultaneously with CVDD is permitted, the voltage for CVDD1 and CVDDT1 must never exceed CVDD until after CVDD has reached a valid voltage. The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 and CVDDT1 should trail CVDD as this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 and CVDDT1 (core constant) ramp up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1 and CVDDT1. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
3a	Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or held in a static state.
3b	The DDR3ACLK, DDR3BCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by item 8.
4	DVDD15 can ramp up within 80 ms of when CVDD1 is valid. RESETSTAT is driven low once the DVDD18 supply is available. All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
5	VDDALV, VDDUSB, VP and VPTX should ramp up within 80 ms of when DVDD15 is valid. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
6	DVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSB, VP and VPTX are valid. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
7	POR must continue to remain low for at least 100 μs after all power rails have stabilized. End power stabilization phase
8	Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
9	RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
10	The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin. Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles. End device initialization phase
11	GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
12	GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.

Figure 11-2 IO-Before-Core Power Sequencing

11.2.2 Power-Down Sequence

The power-down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent an excessive amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail, POR should transition to low to prevent over-current conditions that could possibly impact device reliability.

A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an active reset can affect long term reliability.

11.2.3 Power Supply Decoupling and Bulk Capacitor

To properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are required. Bulk capacitors are used to minimize the effects of low-frequency current transients and decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of power supply decoupling and bulk capacitors see Hardware Design Guide for KeyStone II Devices.

11.2.4 SmartReflex

Increasing the device complexity increases its power consumption. With higher clock rates and increased performance comes an inevitable penalty: increasing leakage currents. Leakage currents are present in any powered circuit, independent of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type and process technology. Higher clock rates also increase dynamic power, which is the power used when transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O activity.

Texas Instruments SmartReflex technology is used to decrease both static and dynamic power consumption while maintaining the device performance. SmartReflex in the 66AK2Hxx device is a feature that allows the core voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each 66AK2Hxx device.

To help maximize performance and minimize power consumption of the device, SmartReflex is required to be implemented. The voltage selection can be accomplished using 4 VCNTL pins or 6 VCNTL pins (depending on power supply device being used), which are used to select the output voltage of the core voltage regulator.

For information on implementation of SmartReflex, see Power Consumption Summary for KeyStone TCI66x Devices and Hardware Design Guide for KeyStone II Devices.

SmartReflex switching characteristics are shown in Table 11-5.

Figure 11-3 SmartReflex 4-Pin 6-Bit VID Interface Timing

11.3.1 Power Domains

The device has several power domains that can be turned on for operation or off to minimize power dissipation. The Global Power Sleep Controller (GPSC) is used to control the power gating of various power domains.

Table 11-6 shows the 66AK2Hxx power domains.

11.3.2 Clock Domains

Clock gating to each logic block is managed by the Local Power Sleep Controllers (LPSCs) of each module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and disable the clocks of that module at the source. For modules that share a clock with other modules, the LPSC controls the clock gating logic for each module.

Table 11-7 shows the 66AK2Hxx clock domains.

11.3.3 PSC Register Memory Map

Table 11-8 shows the PSC Register memory map.

Table 11-9 Reset Types

11.4.1 Power-on Reset

Power-on reset is used to reset the entire device, including the test and emulation logic.

Power-on reset is initiated by the following:

1. POR pin
2. RESETFULL pin

During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. Also a RESETFULL pin is provided to allow reset of the entire device, including the reset-isolated logic, when the device is already powered up. For this reason, the RESETFULL pin, unlike POR, should be driven by the onboard host control other than the power good circuitry. For power-on reset, the Core PLL Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL Controller.

The following sequence must be followed during a power-on reset:

1. Wait for all power supplies to reach normal operating conditions while keeping the POR and RESETFULL pins asserted (driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is deasserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and remain in their reset state until otherwise configured by their respective peripheral. All peripherals that are power-managed are disabled after a power-on reset and must be enabled through the Device State Control Registers (for more details, see Section 10.2.3).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset synchronously. All logic is now reset and RESETSTAT is driven low, indicating that the device is in reset.
3. POR must be held active until all supplies on the board are stable, and then for at least an additional period of time (as specified in Section 11.2.1) for the chip-level PLLs to lock.
4. The POR pin can now be deasserted. Reset-sampled pin values are latched at this point. Then, all chip-level PLLs are taken out of reset, locking sequences begin, and all power-on device initialization processes begin.
5. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time, the DDR3A PLL and DDR3B PLL have already completed their locking sequences and are supplying a valid clock. The system clocks of the PLL controllers are allowed to finish their current cycles and then are paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide-by settings.
6. The device is now out of reset and code execution begins as dictated by the selected boot mode.

11.4.2 Hard Reset

A hard reset will reset everything on the device except the PLLs, test logic, emulation logic, and reset-isolated modules. POR should also remain deasserted during this time.

Hard reset is initiated by the following:

• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer
• Emulation

By default, all the initiators listed above are configured to generate a hard reset. Except for emulation, all of the other three initiators can be configured in the RSCFG Register in the PLL Controller to generate soft resets.

The following sequence must be followed during a hard reset:

1. The RESET pin is asserted (driven low) for a minimum of 24 CLKIN1 cycles. During this time, the RESET signal propagates to all modules (except those specifically mentioned above). To prevent off-chip contention during the warm reset, all I/O must be Hi-Z for modules affected by RESET.
2. Once all logic is reset, RESETSTAT is asserted (driven low) to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not relatched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high).

11.4.3 Soft Reset

A soft reset behaves like a hard reset except that the EMIF16 MMRs, DDR3A EMIF MMRs, PCIe MMRs sticky bits, and external memory content are retained. POR should also remain deasserted during this time.

Soft reset is initiated by the following:

• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer

In the case of a soft reset, the clock logic and the power control logic of the peripherals are not affected and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3A and DDR3B memory controller registers are not reset. If the user places the DDR3A and DDR3B SDRAM in self-refresh mode before invoking the soft reset, the DDR3A and DDR3B SDRAM memory content is retained.

During a soft reset, the following occurs:

1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset propagates through the system. Internal system clocks are not affected. PLLs remain locked.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL Controller pauses system clocks for approximately eight cycles. At this point:
   • The peripherals remain in the state they were in before the soft reset.
   • The states of the Boot Mode configuration pins are preserved as controlled by the DEVSTAT Register.
   • The DDR3A and DDR3B MMRs and PCIe MMRs retain their previous values. Only the DDR3A and DDR3B memory controller and PCIe state machines are reset by the soft reset.
   • The PLL Controller remains in the mode it was in before the soft reset.
   • System clocks are unaffected.

The boot sequence is started after the system clocks are restarted. Because the Boot Mode configuration pins are not latched with a soft reset, the previous values (as shown in the DEVSTAT Register), are used to select the boot mode.

11.4.4 Local Reset

The local reset can be used to reset a particular C66x CorePac without resetting any other device components.

Local reset is initiated by the following:

• LRESET pin
• Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG registers in the PLL Controller. (See Section 11.5.2.8 and Section 8.3.2.)
  • Local reset
  • NMI
  • NMI followed by a time delay and then a local reset for the C66x CorePac selected
  • Hard reset by requesting reset via the PLL Controller
• LPSC MMRs (memory-mapped registers)

For more details see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.

11.4.5 ARM CorePac Reset

The ARM CorePac uses a combination of power-on-reset and module-reset to reset its components, such as the Cortex-A15 processor, memory subsystem, debug logic, and so forth. The ARM CorePac incorporates the PSC to generate resets for its internal modules. Details of reset generation and distribution inside the ARM CorePac can be found in the KeyStone II Architecture ARM CorePac User's Guide.

11.4.6 Reset Priority

If any of the previously mentioned reset sources occur simultaneously, the PLL Controller processes only the highest priority reset request. The reset request priorities are as follows (high to low):

• Power-on reset
• Hard/soft reset

11.4.7 Reset Controller Register

The reset controller registers are part of the PLL Controller MMRs. All 66AK2Hxx device-specific MMRs are covered in Section 11.5.2. For more details on these registers and how to program them, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.

11.4.8 Reset Electrical Data and Timing

Table 11-10 shows the reset timing requirements and Table 11-11 shows the reset switching characteristics.

Figure 11-4 RESETFULL Reset Timing

Figure 11-5 Soft/Hard Reset Timing

Table 11-12 shows the boot configuration timing requirements.

Figure 11-6 Boot Configuration Timing

11.5.1 Main PLL Controller Device-Specific Information

11.5.2 PLL Controller Memory Map

The memory map of the Main PLL controller is shown in Table 11-15. 66AK2Hxx-specific Main PLL controller register definitions can be found in the sections following Table 11-15. For other registers in the table, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.

It is recommended to use read-modify-write sequence to make any changes to the valid bits in the Main PLL controller registers.

Note that only registers documented here are accessible on the 66AK2Hxx. Other addresses in the Main PLL controller memory map including the Reserved registers must not be modified. Furthermore, only the bits within the registers described here are supported.

11.5.3 Main PLL Control Registers

The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the Main PLL controller for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through an unlocking sequence using the KICK0 and KICK1 registers. These registers reset only on a POR reset.

For valid configurable values of the MAINPLLCTL registers, see Section 10.1.4. See Section 10.2.3.4 for the address location of the KICK registers and their locking and unlocking sequences.

See Figure 11-17 and Table 11-25 for MAINPLLCTL0 details and Figure 11-18 and Table 11-26 for MAINPLLCTL1 details.

11.5.4 ARM PLL Control Registers

The ARM PLL uses two chip-level registers (ARMPLLCTL0 and ARMPLLCTL1) without using the Main PLL controller like other PLLs for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. These registers reset only on a POR reset.

For valid configurable values of the ARMPLLCTL registers, see Section 10.1.4. See Section 10.2.3.4 for the address location of the KICK registers and their locking and unlocking sequences.

See Figure 11-19 and Table 11-27 for ARMPLLCTL0 details and Figure 11-20 and Table 11-28 for ARMPLLCTL1 details.

See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the ARM PLL is also controlled by the SECCTL register in the PLL Controller. See Section 11.5.2.1 for more details.

11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing

The Main PLL controller, ARM, SRIO, HyperLink, PCIe, USB clock input timing requirements are shown in Table 11-29.

Figure 11-21 Main PLL Controller, SRIO, HyperLink, PCIe, USB Clock Input Timing

Figure 11-22 Main PLL Transition Time

Figure 11-23 HYP0CLK, HYP1CLK, and PCIECLK Rise and Fall Times

Figure 11-24 USBCLK Rise and Fall Times

11.6.1 DDR3A PLL and DDR3B PLL Control Registers

The DDR3A PLL and DDR3B PLL, which are used to drive the DDR3A PHY and DDR3B PHY for the EMIF, do not use a PLL controller. DDR3A PLL and DDR3B PLL can be controlled using the DDR3APLLCTL0/DDR3BPLLCTL0 and DDR3APLLCTL1/DDR3BPLLCTL1 registers in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configurable values, see Section 10.1.4. See Section 10.2.3.4 for the address location of the registers and locking and unlocking sequences for accessing the registers. These registers are reset on POR only.

The DDR3A PLL and DDR3B PLL control registers are shown in Figure 11-26 and Figure 11-27 and described in Table 11-30 and Table 11-31.

11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information

As shown in Figure 11-25, the output of DDR3A PLL and DDR3B PLL (PLLOUT) is divided by 2 and directly fed to the DDR3A and DDR3B memory controller. During power-on resets, the internal clocks of the DDR3 PLL are affected as described in Section 11.4. The DDR3 PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

11.6.3 DDR3 PLL Input Clock Electrical Data and Timing

Table 11-32 applies to both DDR3A and DDR3B memory interfaces.

Figure 11-28 DDR3 PLL DDRCLK Timing

11.7.1 PASS PLL Local Clock Dividers

The clock signal from the PASS PLL controller is routed to the network coprocessor. The NetCP module has two internal dividers with fixed division ratios, as shown in .

11.7.2 PASS PLL Control Registers

The PASS PLL, which is used to drive the network coprocessor, does not use a PLL controller. PASS PLL can be controlled using the PAPLLCTL0 and PAPLLCTL1 registers in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configuration values, see Section 10.1.4. See Section 10.2.3.4 for the address location of the registers and locking and unlocking sequences for accessing these registers. These registers are reset on POR only.

The PASS PLL control registers are shown in Figure 11-30 and Figure 11-31 and described in Table 11-33 and Table 11-34.

11.7.3 PASS PLL Device-Specific Information

As shown in Figure 11-29, the output of PASS PLL (PLLOUT) is divided by 3 and directly fed to the Network Coprocessor. During power-on resets, the internal clocks of the PASS PLL are affected as described in Section 11.4. The PASS PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any other resets.

11.7.4 PASS PLL Input Clock Electrical Data and Timing

Table 11-35 shows the PASS PLL timing requirements.

Figure 11-32 PASS PLL Timing

11.8.1 External Interrupts Electrical Data and Timing

Table 11-36 shows the NMI and LRESET timing requirements.

Figure 11-33 NMI and LRESET Timing

11.9.1 DDR3 Memory Controller Device-Specific Information

The 66AK2Hxx includes one 64-bit wide, 1.35-V / 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate at 800 mega transfers per second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS.

Due to the complicated nature of the interface, a limited number of topologies are supported to provide a 16-bit, 32-bit, or 64-bit interface.

The DDR3 electrical requirements are fully specified in the DDR JEDEC specification JESD79-3C. Standard DDR3 SDRAMs are available in 8-bit and 16-bit versions allowing for the following bank topologies to be supported by the interface:

• 72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)
• 72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)
• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
• 36-bit: Five 8-bit SDRAMs (including 4 bits of ECC)
• 64-bit: Four 16-bit SDRAMs
• 64-bit: Eight 8-bit SDRAMs
• 32-bit: Two 16-bit SDRAMs
• 32-bit: Four 8-bit SDRAMs
• 16-bit: One 16-bit SDRAM
• 16-bit: Two 8-bit SDRAMs

The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as I²C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible DDR3 devices and provide the printed-circuit board (PCB) solution and guidelines directly to the user.

A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for an indication that the write completes before signaling to master B that the message is ready, when master B attempts to read the software message, the master B read may bypass the master A write. Thus, master B may read stale data and receive an incorrect message.

Some master peripherals (for example, EDMA3 transfer controllers with TCCMOD=0) always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware specification of write-read ordering, it may be necessary to specify data ordering in the software.

If master A does not wait for an indication that a write is complete, it must perform the following workaround:

1. Perform the required write to DDR3 memory space.
2. Perform a dummy write to the DDR3 memory controller module ID and revision register.
3. Perform a dummy read to the DDR3 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in Step 3. The completion of the read in Step 3 ensures that the previous write was done.

11.9.2 DDR3 Slew Rate Control

The DDR3 slew rate is controlled by use of the PHY registers. See the Keystone II Architecture DDR3 Memory Controller User's Guide for details.

11.9.3 DDR3 Memory Controller Electrical Data and Timing

DDR3 Design Requirements for KeyStone Devices specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements are fully specified in the DDR3 JEDEC Specification JESD79-3C. TI has performed the simulation and system characterization to ensure all DDR3 interface timings in this solution are met. Therefore, no electrical data and timing information is supplied here for this interface.

11.10.1 I²C Device-Specific Information

The device includes multiple I²C peripheral modules.

The I²C modules on the 66AK2Hxx may be used by the SoC to control local peripheral ICs (DACs, ADCs, and so forth), communicate with other controllers in a system, or to implement a user interface.

The I²C port supports:

• Compatibility with Philips I²C specification revision 2.1 (January 2000)
• Fast mode up to 400 kbps (no fail-safe I/O buffers)
• Noise filter to remove noise of 50 ns or less
• 7-bit and 10-bit device addressing modes
• Multimaster (transmit/receive) and slave (transmit/receive) functionality
• Events: DMA, interrupt, or polling
• Slew-rate limited open-drain output buffers

Figure 11-34 shows a block diagram of the I²C module.

Figure 11-34 I²C Module Block Diagram

11.10.2 I²C Peripheral Register Description

Table 11-37 lists the I²C registers.

11.10.3 I²C Electrical Data and Timing

Table 11-38 shows the I²C timing requirements and Table 11-39 shows the I²C switching characteristics.

Figure 11-35 I²C Receive Timings

Figure 11-36 I²C Transmit Timings

11.11.1 SPI Electrical Data and Timing

Table 11-40 shows the SPI timing requirements and Table 11-41 shows the SPI switching characteristics.

Figure 11-37 SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode