SBASAF6A October   2021  – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3 ADC Core
        1. 6.3.3.1 ADC Core Calibration
        2. 6.3.3.2 ADC Theory of Operation
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Over-range Detection
        5. 6.3.3.5 Code Error Rate (CER)
        6. 6.3.3.6 Temperature Monitoring Diode
        7. 6.3.3.7 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        5. 6.3.4.5 JESD204C Interface
          1. 6.3.4.5.1  Transport Layer
          2. 6.3.4.5.2  Scrambler
          3. 6.3.4.5.3  Link Layer
          4. 6.3.4.5.4  8B/10B Link Layer
            1. 6.3.4.5.4.1 Data Encoding (8B/10B)
            2. 6.3.4.5.4.2 Multiframes and the Local Multiframe Clock (LMFC)
            3. 6.3.4.5.4.3 Code Group Synchronization (CGS)
            4. 6.3.4.5.4.4 Initial Lane Alignment Sequence (ILAS)
            5. 6.3.4.5.4.5 Frame and Multiframe Monitoring
          5. 6.3.4.5.5  64B/66B Link Layer
            1. 6.3.4.5.5.1 64B/66B Encoding
            2. 6.3.4.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. 6.3.4.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. 6.3.4.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
                2. 6.3.4.5.5.2.1.2 Forward Error Correction (FEC) Mode
            3. 6.3.4.5.5.3 Initial Lane Alignment
            4. 6.3.4.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
          6. 6.3.4.5.6  Physical Layer
            1. 6.3.4.5.6.1 SerDes Pre-Emphasis
          7. 6.3.4.5.7  JESD204C Enable
          8. 6.3.4.5.8  Multi-Device Synchronization and Deterministic Latency
          9. 6.3.4.5.9  Operation in Subclass 0 Systems
          10. 6.3.4.5.10 Alarm Monitoring
            1. 6.3.4.5.10.1 Clock Upset Detection
            2. 6.3.4.5.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1  Serializer Test-Mode Details
        2. 6.4.4.2  PRBS Test Modes
        3. 6.4.4.3  Clock Pattern Mode
        4. 6.4.4.4  Ramp Test Mode
        5. 6.4.4.5  Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6  D21.5 Test Mode
        7. 6.4.4.7  K28.5 Test Mode
        8. 6.4.4.8  Repeated ILA Test Mode
        9. 6.4.4.9  Modified RPAT Test Mode
        10. 6.4.4.10 Calibration Modes and Trimming
          1. 6.4.4.10.1 Foreground Calibration Mode
          2. 6.4.4.10.2 Background Calibration Mode
          3. 6.4.4.10.3 Low-Power Background Calibration (LPBG) Mode
        11. 6.4.4.11 Offset Calibration
        12. 6.4.4.12 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
    6. 6.6 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Initialization Set Up
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Sequencing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.2 JESD204C Modes

The device can be programmed for a number JESD204C output formats. Table 6-14 summarizes the basic operating mode configuration parameters and whether they are user configured or derived.

Table 6-14 ADC09QJ1300 Operating Mode Configuration Parameters
PARAMETERDESCRIPTIONUSER CONFIGURED OR DERIVEDVALUE
JMODEJESD204C operating mode, automatically derives the rest of the JESD204C parametersUser configuredSet by JMODE
RNumber of bits transmitted per lane per ADC core sampling clock cycle. The JESD204C line rate is the sampling clock frequency (fS) times R. This parameter sets the SerDes PLL multiplication factor.DerivedSee Table 6-16, Table 6-17 and Table 6-18
KNumber of frames per multiframe (8B/10B mode)User configuredSet by KM1, see the allowed values in Table 6-16, Table 6-17 and Table 6-18. This parameter is ignored in 64B/66B modes.
ENumber of multiblocks per extended multiblock (64B/66B mode)DerivedAlways set to '1' in ADC09QJ1300. This parameter is ignored in 8B/10B modes.

There are a number of parameters required to define the JESD204C transport layer format, all of which are sent across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the ILAS, however the transport layer uses the same parameters. In the device, most parameters are automatically derived based on the selected JMODE; however, a few are configured by the user. Table 6-15 describes these parameters.

Table 6-15 JESD204C Initial Lane Alignment Sequence Parameters
PARAMETERDESCRIPTIONUSER CONFIGURED OR DERIVEDVALUE
ADJCNTLMFC adjustment amount (not applicable)DerivedAlways 0
ADJDIRLMFC adjustment direction (not applicable)DerivedAlways 0
BIDBank IDDerivedAlways 0
CFNumber of control words per frameDerivedAlways 0
CSControl bits per sampleDerivedAlways set to 0 in ILAS, see Table 6-16, Table 6-17 and Table 6-18 for actual usage
DIDDevice identifier, used to identify the linkUser configuredSet by DID, see Table 6-19
FNumber of octets (bytes) per frame (per lane)DerivedSee Table 6-16, Table 6-17 and Table 6-18
HDHigh-density format (samples split between lanes)DerivedAlways 0
JESDVJESD204 standard revisionDerivedAlways 1
KNumber of frames per multiframeUser configuredSet by the KM1 register
LNumber of serial output lanes per linkDerivedSee Table 6-16, Table 6-17 and Table 6-18
LIDLane identifier for each laneDerivedSee Table 6-19
MNumber of converters used to determine lane bit packing; may not match number of ADC channels in the deviceDerivedSee Table 6-16, Table 6-17 and Table 6-18
NSample resolution (before adding control and tail bits)DerivedSee Table 6-16, Table 6-17 and Table 6-18
N'Bits per sample after adding control and tail bitsDerivedSee Table 6-16, Table 6-17 and Table 6-18
SNumber of samples per converter (M) per frameDerivedSee Table 6-16, Table 6-17 and Table 6-18
SCRScrambler enabledUser configuredSet by SCR
SUBCLASSVDevice subclass versionDerivedAlways 1
RES1Reserved field 1DerivedAlways 0
RES2Reserved field 2DerivedAlways 0
CHKSUMChecksum for ILAS checking (sum of all above parameters modulo 256)DerivedComputed based on parameters in this table

Configuring the device is made easy by using a single configuration parameter called JMODE. Using Table 6-16 for the quad channel device, Table 6-17 for the dual channel device or Table 6-18 for the single channel device, the correct JMODE value can be found for the desired operating mode. The modes listed are the only available operating modes. This tables also gives a range and allowable step size for the K parameter (set by KM1), which sets the multiframe length in number of frames.

Table 6-16 Quad Channel Modes (supported by Quad Channel Device)
OPERATING MODE USER-SPECIFIED PARAMETER DERIVED PARAMETERS INPUT CLOCK RANGE (MHz)
JMODE K
[Min:Step:Max]		 Encoding N CS N’ CF L M F S HD E R
(Fbit / Fclk)
9-Bit, 8B/10B, 8 Lanes 0 4:4:256 8B/10B 9 0 12 0 8 8(1) 8 5 0 — 8 500-1300
9-Bit, 8B/10B, 6 Lanes 1 16:16:256 8B/10B 9 0 12 0 6 4 2 2 1 — 10 500-1300
8-Bit, 8B/10B, 4 Lanes 2 32:32:256 8B/10B 8 0 8 0 4 4 1 1 0 — 10 500-1300
9-Bit, 8B/10B, 4 Lanes 3 32:32:256 8B/10B 9 0 10 0 4 4 5 4 0 — 12.5 500-1300
9-Bit, 64B/66B, 3 Lanes 4 128(2) 64B/66B 9 0 12 0 3 4 2 1 1 1 16.5 500-1040
8-Bit, 64B/66B, 2 Lanes 5 128(2) 64B/66B 8 0 8 0 2 4 2 1 0 1 16.5 500-1040
9-Bit, 64B/66B, 6 Lanes 6 128(2) 64B/66B 9 0 12 0 6 4 2 2 1 1 8.25 500-1300
8-Bit, 64B/66B, 4 Lanes 7 256(2) 64B/66B 8 0 8 0 4 4 1 1 0 1 8.25 500-1300
9-Bit, 64B/66B, 4 Lanes 8 256(2) 64B/66B 9 0 12 0 4 4 3 2 0 3 12.375 500-1300
8-Bit, 8B/10B, 8 Lanes 9 32:32:256 8B/10B 8 0 8 0 8 4 1 2 0 — 5 500-1300
9-Bit, 8B/10B, 8 Lanes 10 32:32:256 8B/10B 9 0 10 0 8 8(1) 5 4 0 — 6.25 500-1300
9-Bit, 64B/66B, 8 Lanes 14 256(2) 64B/66B 9 0 12 0 8 8(1) 3 2 0 3 6.1875 500-1300
(1) M equals L in these modes to allow the samples to be sent in time-order over L lanes without unnecessary buffering. The M parameter does not represent the actual number of converters. Interleave the M sample streams from each link in the receiver to produce the correct sample data; see mode diagrams for more details.
(2) In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K = 8 x 32 x E/F. K is not an actual parameter of the 64B/66B link layer.
Table 6-17 Dual Channel Modes (supported by Quad and Dual-Channel Devices)
OPERATING MODE USER-SPECIFIED PARAMETER DERIVED PARAMETERS INPUT CLOCK RANGE (MHz)
JMODE K
[Min:Step:Max]		 Encoding N CS N’ CF L M F S HD E R
(Fbit / Fclk)
9-Bit, 8B/10B, 4 Lanes 0 4:4:256 8B/10B 9 0 12 0 4 4(1) 8 5 0 — 8 500-1300
9-Bit, 8B/10B, 3 Lanes 1 16:16:256 8B/10B 9 0 12 0 3 2 2 2 1 — 10 500-1300
8-Bit, 8B/10B, 2 Lanes 2 32:32:256 8B/10B 8 0 8 0 2 2 1 1 0 — 10 500-1300
9-Bit, 8B/10B, 2 Lanes 3 32:32:256 8B/10B 9 0 10 0 2 2 5 4 0 — 12.5 500-1300
9-Bit, 64B/66B, 2 Lanes 4 128(2) 64B/66B 9 0 12 0 2 2 2 1 1 1 16.5 500-1040
8-Bit, 64B/66B, 1 Lane 5 128(2) 64B/66B 8 0 8 0 1 2 2 1 0 1 16.5 500-1040
9-Bit, 64B/66B, 3 Lanes 6 128(2) 64B/66B 9 0 12 0 3 2 2 2 1 1 8.25 500-1300
8-Bit, 64B/66B, 2 Lanes 7 256(2) 64B/66B 8 0 8 0 2 2 1 1 0 1 8.25 500-1300
9-Bit, 64B/66B, 2 Lanes 8 256(2) 64B/66B 9 0 12 0 2 2 3 2 0 3 12.375 500-1300
8-Bit, 8B/10B, 4 Lanes 9 32:32:256 8B/10B 8 0 8 0 3 2 1 2 0 — 5 500-1300
9-Bit, 8B/10B, 4 Lanes 10 32:32:256 8B/10B 9 0 10 0 4 4(1) 5 4 0 — 6.25 500-1300
9-Bit, 8B/10B, 8 Lanes 11 4:4:256 8B/10B 9 0 12 0 8 8(1) 8 5 0 — 4 500-1300
8-Bit, 8B/10B, 8 Lanes 12 32:32:256 8B/10B 8 0 8 0 8 2 1 4 0 — 2.5 500-1300
9-Bit, 8B/10B, 8 Lanes 13 32:32:256 8B/10B 9 0 10 0 8 8(1) 5 4 0 — 3.125 500-1300
9-Bit, 64B/66B, 4 Lanes 14 256(2) 64B/66B 9 0 12 0 4 4(1) 3 2 0 3 6.1875 500-1300
9-Bit, 64B/66B, 8 Lanes 15 256(2) 64B/66B 9 0 12 0 8 8(1) 3 2 2 3 3.09375 500-1300
(1) M equals L in these modes to allow the samples to be sent in time-order over L lanes without unnecessary buffering. The M parameter does not represent the actual number of converters. Interleave the M sample streams from each link in the receiver to produce the correct sample data; see mode diagrams for more details.
(2) In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K = 8 x 32 x E/F. K is not an actual parameter of the 64B/66B link layer.
Table 6-18 Single Channel Modes (supported by Quad, Dual and Single channel devices)
OPERATING MODE USER-SPECIFIED PARAMETER DERIVED PARAMETERS INPUT CLOCK RANGE (MHz)
JMODE K
[Min:Step:Max]		 Encoding N CS N’ CF L M F S HD E R
(Fbit / Fclk)
9-Bit, 8B/10B, 2 Lanes 0 4:4:256 8B/10B 9 0 12 0 2 2(1) 8 5 0 — 8 500-1300
9-Bit, 8B/10B, 2 Lanes 1 16:16:256 8B/10B 9 0 12 0 2 1 2 2 1 — 10 500-1300
8-Bit, 8B/10B, 2 Lanes 2 32:32:256 8B/10B 8 0 8 0 1 4 1 1 0 — 10 500-1300
9-Bit, 8B/10B, 1 Lane 3 32:32:256 8B/10B 9 0 10 0 1 4 5 4 0 — 12.5 500-1300
9-Bit, 64B/66B, 1 Lane 4 128(2) 64B/66B 9 0 12 0 1 4 2 1 1 1 16.5 500-1040
8-Bit, 64B/66B, 1 Lanes 5 128(2) 64B/66B 8 0 8 0 1 4 2 1 0 1 16.5 500-1040
9-Bit, 64B/66B, 2 Lanes 6 128(2) 64B/66B 9 0 12 0 2 4 2 2 1 1 8.25 500-1300
8-Bit, 64B/66B, 1 Lane 7 256(2) 64B/66B 8 0 8 0 1 4 1 1 0 1 8.25 500-1300
9-Bit, 64B/66B, 1 Lane 8 256(2) 64B/66B 9 0 12 0 1 4 3 2 0 3 12.375 500-1300
8-Bit, 8B/10B, 2 Lanes 9 32:32:256 8B/10B 8 0 8 0 2 4 1 2 0 — 5 500-1300
9-Bit, 8B/10B, 2 Lanes 10 32:32:256 8B/10B 9 0 10 0 2 2(1) 5 4 0 — 6.25 500-1300
9-Bit, 8B/10B, 4 Lanes 11 4:4:256 8B/10B 9 0 12 0 4 4(1) 8 5 0 — 4 500-1300
8-Bit, 8B/10B, 4 Lanes 12 32:32:256 8B/10B 8 0 8 0 4 1 1 4 0 — 2.5 500-1300
9-Bit, 8B/10B, 4 Lanes 13 32:32:256 8B/10B 9 0 10 0 4 4(1) 5 4 0 — 3.125 500-1300
9-Bit, 64B/66B, 2 Lanes 14 256(2) 64B/66B 9 0 12 0 2 2(1) 3 2 0 3 6.1875 500-1300
9-Bit, 64B/66B, 4 Lanes 15 256(2) 64B/66B 9 0 12 0 4 4(1) 3 2 2 3 3.09375 500-1300
(1) M equals L in these modes to allow the samples to be sent in time-order over L lanes without unnecessary buffering. The M parameter does not represent the actual number of converters. Interleave the M sample streams from each link in the receiver to produce the correct sample data; see mode diagrams for more details.
(2) In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K = 8 x 32 x E/F. K is not an actual parameter of the 64B/66B link layer.

The quad and dual channel devices have a total of 8 high-speed output drivers and the single channel device a total of 4 high-speed output drivers. The lanes and their derived configuration parameters are described in Table 6-19. For a specified JMODE, the lowest indexed lanes are used and the higher indexed lanes are automatically powered down. Always route the lowest indexed lanes to the logic device.

Table 6-19 ADC09QJ1300 Lane Assignment and Parameters
DEVICE PIN DESIGNATIONDevicesDID (User Configured)LID (Derived)
D0±AllSet by DID0
D1±AllSet by DID1
D2±AllSet by DID2
D3±AllSet by DID3
D4±Quad/Dual onlySet by DID4
D5±Quad/Dual onlySet by DID5
D6±Quad/Dual onlySet by DID6
D7±Quad/Dual onlySet by DID7