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ADC09SJ1300

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Single-channel, 9-bit, 1.3-GSPS analog-to-digital converter (ADC) with JESD204C interface

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Data sheet

ADC09SJ1300

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 1300 Resolution (bps) 9 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 940 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (bit) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1300 Resolution (bps) 9 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 940 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (bit) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • ADC Core:
    • Resolution: 9 Bit
    • Maximum sampling rate: 1.3GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 53.5dBFS
    • ENOB (100 MHz): 8.5 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20dBFS): –143dBFS
  • Full-scale input voltage: 80 mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS):
    • Quad Channel: 450mW / channel
    • Dual channel: 625mW / channel
    • Single channel: 940mW
  • Power supplies: 1.1V, 1.9V
  • ADC Core:
    • Resolution: 9 Bit
    • Maximum sampling rate: 1.3GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 53.5dBFS
    • ENOB (100 MHz): 8.5 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20dBFS): –143dBFS
  • Full-scale input voltage: 80 mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS):
    • Quad Channel: 450mW / channel
    • Dual channel: 625mW / channel
    • Single channel: 940mW
  • Power supplies: 1.1V, 1.9V

ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
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* Data sheet ADC09xJ1300 Quad, Dual, Single Channel, 1.3GSPS, 9-bit Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) PDF | HTML 22 Oct 2024

Design & development

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Evaluation board

ADC09QJ1300EVM — ADC09QJ1300 evaluation module for quad-channel, 9-bit, 1.3-GSPS ADC with JESD204C interface

The ADC09QJ1300 evaluation module (EVM) allows for the evaluation of the ADC09QJ1300-Q1 device. ADC09QJ1300-Q1 is a low-power, 9-bit, quad-channel, 1.3-GSPS analog-to-digital converter (ADC) with a buffered analog input and integrated digital down converter with on-chip PLL, which features a (...)

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Evaluation board

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The TSW12QJ1600 evaluation module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 gigasample per second (GSPS) with four analog input channels.

This design (...)

User guide: PDF
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ADC12QJ1600 IBIS-AMI Model

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