SBASAF6A October   2021  – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3 ADC Core
        1. 6.3.3.1 ADC Core Calibration
        2. 6.3.3.2 ADC Theory of Operation
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Over-range Detection
        5. 6.3.3.5 Code Error Rate (CER)
        6. 6.3.3.6 Temperature Monitoring Diode
        7. 6.3.3.7 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        5. 6.3.4.5 JESD204C Interface
          1. 6.3.4.5.1  Transport Layer
          2. 6.3.4.5.2  Scrambler
          3. 6.3.4.5.3  Link Layer
          4. 6.3.4.5.4  8B/10B Link Layer
            1. 6.3.4.5.4.1 Data Encoding (8B/10B)
            2. 6.3.4.5.4.2 Multiframes and the Local Multiframe Clock (LMFC)
            3. 6.3.4.5.4.3 Code Group Synchronization (CGS)
            4. 6.3.4.5.4.4 Initial Lane Alignment Sequence (ILAS)
            5. 6.3.4.5.4.5 Frame and Multiframe Monitoring
          5. 6.3.4.5.5  64B/66B Link Layer
            1. 6.3.4.5.5.1 64B/66B Encoding
            2. 6.3.4.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. 6.3.4.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. 6.3.4.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
                2. 6.3.4.5.5.2.1.2 Forward Error Correction (FEC) Mode
            3. 6.3.4.5.5.3 Initial Lane Alignment
            4. 6.3.4.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
          6. 6.3.4.5.6  Physical Layer
            1. 6.3.4.5.6.1 SerDes Pre-Emphasis
          7. 6.3.4.5.7  JESD204C Enable
          8. 6.3.4.5.8  Multi-Device Synchronization and Deterministic Latency
          9. 6.3.4.5.9  Operation in Subclass 0 Systems
          10. 6.3.4.5.10 Alarm Monitoring
            1. 6.3.4.5.10.1 Clock Upset Detection
            2. 6.3.4.5.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1  Serializer Test-Mode Details
        2. 6.4.4.2  PRBS Test Modes
        3. 6.4.4.3  Clock Pattern Mode
        4. 6.4.4.4  Ramp Test Mode
        5. 6.4.4.5  Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6  D21.5 Test Mode
        7. 6.4.4.7  K28.5 Test Mode
        8. 6.4.4.8  Repeated ILA Test Mode
        9. 6.4.4.9  Modified RPAT Test Mode
        10. 6.4.4.10 Calibration Modes and Trimming
          1. 6.4.4.10.1 Foreground Calibration Mode
          2. 6.4.4.10.2 Background Calibration Mode
          3. 6.4.4.10.3 Low-Power Background Calibration (LPBG) Mode
        11. 6.4.4.11 Offset Calibration
        12. 6.4.4.12 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
    6. 6.6 SPI_Register_Map Registers
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Initialization Set Up
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Sequencing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Short Transport Test Pattern

Short transport test patterns send a predefined octet format that repeats every frame. The short transport test patterns for each JMODE are defined in this section.

Table 6-38 Short Transport Test Pattern for JMODE 0
OCTET01234567
NIBBLE0123456789101112131415
D00xF010xF020xF030xF040xF05T
D10xE110xE120xE130xE140xE15T
D2 (Dual or Quad only)0xD210xD220xD230xD240xD25T
D3 (Dual or Quad only)0xC310xC320xC330xC340xC35T
D4 (Quad only)0xB410xB420xB430xB440xB45T
D5 (Quad only)0xA510xA520xA530xA540xA55T
D6 (Quad only)0x9610x9620x9630x9640x965T
D7 (Quad only)0x8710x8720x8730x8740x875T
Table 6-39 Short Transport Test Pattern for JMODE 1
OCTET01
NIBBLE0123
D00xF010xF
D10x020xE1
D2 (Dual or Quad only)0x10xE12
D3 (Quad only)0xD210xD
D4 (Quad only)0x220xC3
D5 (Quad only)0x10xC32
Table 6-40 Short Transport Test Pattern for JMODE 2
OCTET0
NIBBLE01
D00x01
D1 (Dual or Quad only)0x11
D2 (Quad only)0x21
D3 (Quad only)0x31
Table 6-41 Short Transport Test Pattern for JMODE 3
OCTET01234
NIBBLE0123456789
D00x3010x3020x3030x304
D1 (Dual or Quad only)0x2110x2120x2130x214
D2 (Quad only)0x1210x1220x1230x124
D3 (Quad only)0x0310x0320x0330x034
Table 6-42 Short Transport Test Pattern for JMODE 4
OCTET01
NIBBLE0123
D00xF010xE
D1 (Dual or Quad only)0x110xD2
D2 (Quad only)0x10xC31
Table 6-43 Short Transport Test Pattern for JMODE 5
OCTET01
NIBBLE0123
D00x010x11
D1 (Quad only)0x210x31
Table 6-44 Short Transport Test Pattern for JMODE 6
OCTET01
NIBBLE0123
D00xF010xF
D10x020xE1
D2 (Dual or Quad only)0x10xE12
D3 (Quad only)0xD210xD
D4 (Quad only)0x220xC3
D5 (Quad only)0x10xC32
Table 6-45 Short Transport Test Pattern for JMODE 7
OCTET0
NIBBLE01
D00x01
D1 (Dual or Quad only)0x11
D2 (Quad only)0x21
D3 (Quad only)0x31
Table 6-46 Short Transport Test Pattern for JMODE 8
OCTET012
NIBBLE012345
D00xF010xF02
D1 (Dual or Quad only)0xE110xE12
D2 (Quad only)0xD210xD22
D3 (Quad only)0xC310xC32
Table 6-47 Short Transport Test Pattern for JMODE 9
OCTET0
NIBBLE01
D00x01
D10x02
D2 (Dual or Quad only)0x11
D3 (Dual or Quad only)0x12
D4 (Quad only)0x21
D5 (Quad only)0x22
D6 (Quad only)0x31
D7 (Quad only)0x32
Table 6-48 Short Transport Test Pattern for JMODE 10
OCTET01234
NIBBLE0123456789
D00x3010x3020x3030x304
D10x2110x2120x2130x214
D2 (Dual or Quad only)0x1210x1220x1230x124
D3 (Dual or Quad only)0x0310x0320x0330x034
D4 (Quad only)0x3410x3420x3430x344
D5 (Quad only)0x2510x2520x2530x254
D6 (Quad only)0x1610x1620x1630x164
D7 (Quad only)0x0710x0720x0730x074
Table 6-49 Short Transport Test Pattern for JMODE 11
OCTET01234567
NIBBLE0123456789101112131415
D00xF010xF020xF030xF040xF05T
D10xE110xE120xE130xE140xE15T
D20xD210xD220xD230xD240xD25T
D30xC310xC320xC330xC340xC35T
D4 (Dual only)0xB410xB420xB430xB440xB45T
D5 (Dual only)0xA510xA520xA530xA540xA55T
D6 (Dual only)0x9610x9620x9630x9640x965T
D7 (Dual only)0x8710x8720x8730x8740x875T
Table 6-50 Short Transport Test Pattern for JMODE 12
OCTET0
NIBBLE01
D00x01
D10x02
D20x03
D30x04
D4 (Dual only)0x11
D5 (Dual only)0x12
D6 (Dual only)0x13
D7 (Dual only)0x14
Table 6-51 Short Transport Test Pattern for JMODE 13
OCTET01234
NIBBLE0123456789
D00x3010x3020x3030x304
D10x2110x2120x2130x214
D20x1210x1220x1230x124
D30x0310x0320x0330x034
D4 (Dual only)0x3410x3420x3430x344
D5 (Dual only)0x2510x2520x2530x254
D6 (Dual only)0x1610x1620x1630x164
D7 (Dual only)0x0710x0720x0730x074
Table 6-52 Short Transport Test Pattern for JMODE 14
OCTET012
NIBBLE012345
D00xF010xF02
D10xE110xE12
D2 (Dual or Quad only)0xD210xD22
D3 (Dual or Quad only)0xC310xC32
D4 (Quad only)0xB410xB42
D5 (Quad only)0xA510xA52
D6 (Quad only)0x9610x962
D7 (Quad only)0x8710x872
Table 6-53 Short Transport Test Pattern for JMODE 15
OCTET012
NIBBLE012345
D00xF010xF02
D10xE110xE12
D20xD210xD22
D30xC310xC32
D4 (Dual only)0xB410xB42
D5 (Dual only)0xA510xA52
D6 (Dual only)0x9610x962
D7 (Dual only)0x8710x872