SBASAF6A October   2021  – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3 ADC Core
        1. 6.3.3.1 ADC Core Calibration
        2. 6.3.3.2 ADC Theory of Operation
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Over-range Detection
        5. 6.3.3.5 Code Error Rate (CER)
        6. 6.3.3.6 Temperature Monitoring Diode
        7. 6.3.3.7 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        5. 6.3.4.5 JESD204C Interface
          1. 6.3.4.5.1  Transport Layer
          2. 6.3.4.5.2  Scrambler
          3. 6.3.4.5.3  Link Layer
          4. 6.3.4.5.4  8B/10B Link Layer
            1. 6.3.4.5.4.1 Data Encoding (8B/10B)
            2. 6.3.4.5.4.2 Multiframes and the Local Multiframe Clock (LMFC)
            3. 6.3.4.5.4.3 Code Group Synchronization (CGS)
            4. 6.3.4.5.4.4 Initial Lane Alignment Sequence (ILAS)
            5. 6.3.4.5.4.5 Frame and Multiframe Monitoring
          5. 6.3.4.5.5  64B/66B Link Layer
            1. 6.3.4.5.5.1 64B/66B Encoding
            2. 6.3.4.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. 6.3.4.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. 6.3.4.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
                2. 6.3.4.5.5.2.1.2 Forward Error Correction (FEC) Mode
            3. 6.3.4.5.5.3 Initial Lane Alignment
            4. 6.3.4.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
          6. 6.3.4.5.6  Physical Layer
            1. 6.3.4.5.6.1 SerDes Pre-Emphasis
          7. 6.3.4.5.7  JESD204C Enable
          8. 6.3.4.5.8  Multi-Device Synchronization and Deterministic Latency
          9. 6.3.4.5.9  Operation in Subclass 0 Systems
          10. 6.3.4.5.10 Alarm Monitoring
            1. 6.3.4.5.10.1 Clock Upset Detection
            2. 6.3.4.5.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1  Serializer Test-Mode Details
        2. 6.4.4.2  PRBS Test Modes
        3. 6.4.4.3  Clock Pattern Mode
        4. 6.4.4.4  Ramp Test Mode
        5. 6.4.4.5  Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6  D21.5 Test Mode
        7. 6.4.4.7  K28.5 Test Mode
        8. 6.4.4.8  Repeated ILA Test Mode
        9. 6.4.4.9  Modified RPAT Test Mode
        10. 6.4.4.10 Calibration Modes and Trimming
          1. 6.4.4.10.1 Foreground Calibration Mode
          2. 6.4.4.10.2 Background Calibration Mode
          3. 6.4.4.10.3 Low-Power Background Calibration (LPBG) Mode
        11. 6.4.4.11 Offset Calibration
        12. 6.4.4.12 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
    6. 6.6 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Initialization Set Up
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Sequencing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics: Power Consumption

typical values at TA = 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 97 MHz, AIN = –1 dBFS, fCLK = 1.3 GHz, filtered 1-VPP sine-wave clock applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVA19 1.9-V analog supply current Power mode 1a: Quad channel, JMODE 0 (9-bit, 8 lanes, 8B/10B encoding), FG calibration, PLL_EN = 0, fS = 1.3 GSPS, High Performance Mode 667 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 576 mA
IVD11 1.1-V digital supply current 600 mA
PDIS Power dissipation 2.56 W
IVA19 1.9-V analog supply current Power mode 1b: Duad channel, JMODE 0 (9-bit, 8 lanes, 8B/10B encoding), FG calibration, PLL_EN = 0, fS = 1.3 GSPS, High Performance Mode 385 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 452 mA
IVD11 1.1-V digital supply current 379 mA
PDIS Power dissipation 1.64 W
IVA19 1.9-V analog supply current Power mode 1c: Single channel, JMODE 0 (9-bit, 8 lanes, 8B/10B encoding), FG calibration, PLL_EN = 0, fS = 1.3 GSPS, High Performance Mode 257 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 419 mA
IVD11 1.1-V digital supply current 236 mA
PDIS Power dissipation 1.2 W
IVA19 1.9-V analog supply current Power mode 2a: Quad channel, JMODE 8 (9-bit, 4 lanes, 64B/66B encoding), LPBG calibration, PLL_EN = 0, fS = 1.0 GSPS, Low Power Mode 565 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 400 mA
IVD11 1.1-V digital supply current 387 mA
PDIS Power dissipation 1.95(1) W
IVA19 1.9-V analog supply current Power mode 2b: Dual channel, JMODE 8 (9-bit, 4 lanes, 64B/66B encoding), LPBG calibration, PLL_EN = 0, fS = 1.0 GSPS, Low Power Mode 347 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 344 mA
IVD11 1.1-V digital supply current 239 mA
PDIS Power dissipation 1.3(1) W
IVA19 1.9-V analog supply current Power mode 2c: Single channel, JMODE 8 (9-bit, 4 lanes, 64B/66B encoding), LPBG calibration, PLL_EN = 0, fS = 1.0 GSPS, Low Power Mode 240 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 322 mA
IVD11 1.1-V digital supply current 179 mA
PDIS Power dissipation 1.01(1) W
IVA19 1.9-V analog supply current Power mode 3a: Quad channel, JMODE 8 (9-bit, 4 lanes, 64B/66B encoding), LPBG calibration, PLL_EN = 1, PLLREF_SE = 1, fREF= 50 MHz, TRIGOUT± enabled, fS = 1.0 GSPS, Low Power Mode 565 mA
IVPLL19 PLL analog supply current 60 mA
IVREFO PLLREFO± analog supply current 12 mA
IVTRIG TRIGOUT± analog supply current 5.4 mA
IVA11 1.1-V analog supply current 375 mA
IVD11 1.1-V digital supply current 387 mA
PDIS Power dissipation 2.07(1) W
IVA19 1.9-V analog supply current Power mode 3b: Dual channel, JMODE 8 (9-bit, 4 lanes, 64B/66B encoding), LPBG calibration, PLL_EN = 1, PLLREF_SE = 1, fREF= 50 MHz, TRIGOUT± enabled, fS = 1.0 GSPS, Low Power Mode 348 mA
IVPLL19 PLL analog supply current 58 mA
IVREFO PLLREFO± analog supply current 12 mA
IVTRIG TRIGOUT± analog supply current 5.4 mA
IVA11 1.1-V analog supply current 332 mA
IVD11 1.1-V digital supply current 239 mA
PDIS Power dissipation 1.45(1) W
IVA19 1.9-V analog supply current Power mode 3c: Single channel, JMODE 8 (9-bit, 4 lanes, 64B/66B encoding), LPBG calibration, PLL_EN = 1, PLLREF_SE = 1, fREF= 50 MHz, TRIGOUT± enabled, fS = 1.0 GSPS, Low Power Mode 241 mA
IVPLL19 PLL analog supply current 59 mA
IVREFO PLLREFO± analog supply current 12.5 mA
IVTRIG TRIGOUT± analog supply current 5.4 mA
IVA11 1.1-V analog supply current 312 mA
IVD11 1.1-V digital supply current 178 mA
PDIS Power dissipation 1.15(1) W
IVA19 1.9-V analog supply current Power mode 4a: Quad channel, JMODE 7 (8-bit, 4 lanes, 64B/66B encoding), FG calibration, PLL_EN = 0, fS = 1.0 GSPS, Low Power Mode 540 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 371 mA
IVD11 1.1-V digital supply current 295 mA
PDIS Power dissipation 1.74 W
IVA19 1.9-V analog supply current Power mode 4b: Dual channel, JMODE 7 (8-bit, 4 lanes, 64B/66B encoding), FG calibration, PLL_EN = 0, fS = 1.0 GSPS, Low Power Mode 335 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 323 mA
IVD11 1.1-V digital supply current 180 mA
PDIS Power dissipation 1.19 W
IVA19 1.9-V analog supply current Power mode 4c: Single channel, JMODE 7 (8-bit, 4 lanes, 64B/66B encoding), FG calibration, PLL_EN = 0, fS = 1.0 GSPS, Low Power Mode 228 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 301 mA
IVD11 1.1-V digital supply current 136 mA
PDIS Power dissipation 0.91 W
IVA19 1.9-V analog supply current Power mode 5a: Quad channel, JMODE 0 (9-bit, 8 lanes, 8B/10B encoding), BG calibration, PLL_EN = 1, PLLREF_SE = 0, fREF= 50 MHz, TRIGOUT± enabled, fS = 1.3 GSPS, High Performance Mode 815 mA
IVPLL19 PLL analog supply current 60 mA
IVREFO PLLREFO± analog supply current 13 mA
IVTRIG TRIGOUT± analog supply current 6 mA
IVA11 1.1-V analog supply current 607 mA
IVD11 1.1-V digital supply current 580 mA
PDIS Power dissipation 3.04 W
IVA19 1.9-V analog supply current Power mode 5b: Dual channel, JMODE 0 (9-bit, 8 lanes, 8B/10B encoding), BG calibration, PLL_EN = 1, PLLREF_SE = 0, fREF= 50 MHz, TRIGOUT± enabled, fS = 1.3 GSPS, High Performance Mode 528 mA
IVPLL19 PLL analog supply current 59 mA
IVREFO PLLREFO± analog supply current 12.5 mA
IVTRIG TRIGOUT± analog supply current 5.4 mA
IVA11 1.1-V analog supply current 504 mA
IVD11 1.1-V digital supply current 380 mA
PDIS Power dissipation 2.13 W
IVA19 1.9-V analog supply current Power mode 5c: Single channel, JMODE 0 (9-bit, 8 lanes, 8B/10B encoding), BG calibration, PLL_EN = 1, PLLREF_SE = 0, fREF= 50 MHz, TRIGOUT± enabled, fS = 1.3 GSPS, High Performance Mode 392 mA
IVPLL19 PLL analog supply current 59 mA
IVREFO PLLREFO± analog supply current 13 mA
IVTRIG TRIGOUT± analog supply current 5.4 mA
IVA11 1.1-V analog supply current 470 mA
IVD11 1.1-V digital supply current 245 mA
PDIS Power dissipation 1.68 W
IVA19 1.9-V analog supply current Power mode 6: Power-down enabled (PD = 1) 48 mA
IVPLL19 PLL analog supply current 0 mA
IVREFO PLLREFO± analog supply current 0 mA
IVTRIG TRIGOUT± analog supply current 0 mA
IVA11 1.1-V analog supply current 32 mA
IVD11 1.1-V digital supply current 17 mA
PDIS Power dissipation 0.155 W
(1) Low-power background (LPBG) calibration supply current and power dissipation numbers are in the calibration sleep state. The power dissipation in this mode increases to the background (BG) calibration power consumption during the calibration state. The sleep period can be controlled by the user and long sleep periods will average out the calibration state power dissipation contribution.