SBASAF6A October   2021  – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3 ADC Core
        1. 6.3.3.1 ADC Core Calibration
        2. 6.3.3.2 ADC Theory of Operation
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Over-range Detection
        5. 6.3.3.5 Code Error Rate (CER)
        6. 6.3.3.6 Temperature Monitoring Diode
        7. 6.3.3.7 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        5. 6.3.4.5 JESD204C Interface
          1. 6.3.4.5.1  Transport Layer
          2. 6.3.4.5.2  Scrambler
          3. 6.3.4.5.3  Link Layer
          4. 6.3.4.5.4  8B/10B Link Layer
            1. 6.3.4.5.4.1 Data Encoding (8B/10B)
            2. 6.3.4.5.4.2 Multiframes and the Local Multiframe Clock (LMFC)
            3. 6.3.4.5.4.3 Code Group Synchronization (CGS)
            4. 6.3.4.5.4.4 Initial Lane Alignment Sequence (ILAS)
            5. 6.3.4.5.4.5 Frame and Multiframe Monitoring
          5. 6.3.4.5.5  64B/66B Link Layer
            1. 6.3.4.5.5.1 64B/66B Encoding
            2. 6.3.4.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. 6.3.4.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. 6.3.4.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
                2. 6.3.4.5.5.2.1.2 Forward Error Correction (FEC) Mode
            3. 6.3.4.5.5.3 Initial Lane Alignment
            4. 6.3.4.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
          6. 6.3.4.5.6  Physical Layer
            1. 6.3.4.5.6.1 SerDes Pre-Emphasis
          7. 6.3.4.5.7  JESD204C Enable
          8. 6.3.4.5.8  Multi-Device Synchronization and Deterministic Latency
          9. 6.3.4.5.9  Operation in Subclass 0 Systems
          10. 6.3.4.5.10 Alarm Monitoring
            1. 6.3.4.5.10.1 Clock Upset Detection
            2. 6.3.4.5.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1  Serializer Test-Mode Details
        2. 6.4.4.2  PRBS Test Modes
        3. 6.4.4.3  Clock Pattern Mode
        4. 6.4.4.4  Ramp Test Mode
        5. 6.4.4.5  Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6  D21.5 Test Mode
        7. 6.4.4.7  K28.5 Test Mode
        8. 6.4.4.8  Repeated ILA Test Mode
        9. 6.4.4.9  Modified RPAT Test Mode
        10. 6.4.4.10 Calibration Modes and Trimming
          1. 6.4.4.10.1 Foreground Calibration Mode
          2. 6.4.4.10.2 Background Calibration Mode
          3. 6.4.4.10.3 Low-Power Background Calibration (LPBG) Mode
        11. 6.4.4.11 Offset Calibration
        12. 6.4.4.12 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
    6. 6.6 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Initialization Set Up
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Sequencing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics: AC Specifications

typical values at TA = 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 97 MHz, AIN = –1 dBFS, fCLK = 1.3 GHz, filtered 1-VPP sine-wave clock applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FPBW Full-power input bandwidth (–3 dB)(1) Foreground calibration 6 GHz
Background calibration 6
XTALK Channel-to-channel crosstalk
(Quad and dual channel only)		 Aggressor = 400 MHz, –1 dBFS –72 dB
Aggressor = 1 GHz, –1 dBFS –65
Aggressor = 3 GHz, –1 dBFS –62
CER Code error rate Maximum CER, does not include JESD204C interface BER 10–18 Errors/ sample
tORR Overrange recovery time Time from an overdriven input to accurate conversion after a step from a ±1.2 VPP-DIFF overdriven input stepped to 0 VPP-DIFF. 1 tCLK cycles
NOISEDC DC input noise standard deviation No input, foreground calibration, excludes DC offset 0.38 LSB
NSD Noise spectral density Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS –142.2 dBFS/Hz
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS –142
NF Noise figure, ZS = 100 Ω Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS 31.8 dB
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS 32
SNR Signal-to-noise ratio, excluding DC, HD2 to HD9 fIN = 97 MHz AIN = –1 dBFS 53.5 dBFS
AIN = –3 dBFS 53.5
AIN = –12 dBFS 54
AIN = –3 dBFS, VFS = 1.0 VPP 54
fIN = 497 MHz AIN = –1 dBFS 53.5
AIN = –3 dBFS 53.5
AIN = –12 dBFS 53.7
fIN = 997 MHz AIN = –1 dBFS 51 53.4
AIN = –3 dBFS 53.5
AIN = –12 dBFS 53.8
AIN = –3 dBFS, VFS = 1.0 VPP 53.8
fIN = 1797 MHz AIN = –1 dBFS 53.2
AIN = –3 dBFS 53.4
AIN = –12 dBFS 53.7
fIN = 2697 MHz AIN = –1 dBFS 52.3
AIN = –3 dBFS 53.1
AIN = –12 dBFS 53.6
fIN = 3497 MHz AIN = –1 dBFS 52.4
AIN = –3 dBFS 52.8
AIN = –12 dBFS 53.5
SINAD Signal-to-noise and distortion ratio, excluding DC offset fIN = 97 MHz AIN = –1 dBFS 52.9 dBFS
AIN = –3 dBFS 53.3
AIN = –12 dBFS 53.6
AIN = –3 dBFS, VFS = 1.0 VPP 53.6
fIN = 497 MHz AIN = –1 dBFS 53.0
AIN = –3 dBFS 53.4
AIN = –12 dBFS 53.9
fIN = 997 MHz AIN = –1 dBFS 51 53.1
AIN = –3 dBFS 53.3
AIN = –12 dBFS 53.8
AIN = –3 dBFS, VFS = 1.0 VPP 53.6
fIN = 1797 MHz AIN = –1 dBFS 52.1
AIN = –3 dBFS 53.0
AIN = –12 dBFS 53.6
fIN = 2697 MHz AIN = –1 dBFS 49.5
AIN = –3 dBFS 51.7
AIN = –12 dBFS 53.6
fIN = 3497 MHz AIN = –1 dBFS 47.1
AIN = –3 dBFS 50.6
AIN = –12 dBFS 53.5
ENOB Effective number of bits, excluding DC offset fIN = 97 MHz AIN = –1 dBFS 8.5 bits
AIN = –3 dBFS 8.6
AIN = –12 dBFS 8.6
AIN = –3 dBFS, VFS = 1.0 VPP 8.6
fIN = 497 MHz AIN = –1 dBFS 8.5
AIN = –3 dBFS 8.5
AIN = -12 dBFS 8.5
fIN = 997 MHz AIN = –1 dBFS 8.1 8.5
AIN = –3 dBFS 8.6
AIN = –12 dBFS 8.6
AIN = –3 dBFS, VFS = 1.0 VPP 8.6
fIN = 1797 MHz AIN = –1 dBFS 8.4
AIN = –3 dBFS 8.5
AIN = –12 dBFS 8.6
fIN = 2697 MHz AIN = –1 dBFS 7.9
AIN = –3 dBFS 8.3
AIN = –12 dBFS 8.6
fIN = 3497 MHz AIN = –1 dBFS 7.5
AIN = –3 dBFS 8.1
AIN = –12 dBFS 8.6
SFDR Spurious-free dynamic range fIN = 97 MHz AIN = –1 dBFS 64 dBFS
AIN = –3 dBFS 68
AIN = –12 dBFS 76
AIN = –3 dBFS, VFS = 1.0 VPP 67
fIN = 497 MHz AIN = –1 dBFS 66
AIN = –3 dBFS 66
AIN = –12 dBFS 76
fIN = 997 MHz AIN = –1 dBFS 55 67
AIN = –3 dBFS 69
AIN = –12 dBFS 77
AIN = –3 dBFS, VFS = 1.0 VPP 69
fIN = 1797 MHz AIN = –1 dBFS 61
AIN = –3 dBFS 67
AIN = –12 dBFS 76
fIN = 2697 MHz AIN = –1 dBFS 54
AIN = –3 dBFS 60
AIN = –12 dBFS 76
fIN = 3497 MHz AIN = –1 dBFS 49
AIN = –3 dBFS 56
AIN = –12 dBFS 76
HD2 2nd-order harmonic distortion fIN = 97 MHz AIN = –1 dBFS –64 dBFS
AIN = –3 dBFS –70
AIN = –12 dBFS –81
AIN = –3 dBFS, VFS = 1.0 VPP –67
fIN = 497 MHz AIN = –1 dBFS –67
AIN = –3 dBFS –67
AIN = –12 dBFS –81
fIN = 997 MHz AIN = –1 dBFS –68 –55
AIN = –3 dBFS –71
AIN = –12 dBFS –80
AIN = –3 dBFS, VFS = 1.0 VPP –70
fIN = 1797 MHz AIN = –1 dBFS –65
AIN = –3 dBFS –68
AIN = –12 dBFS –80
fIN = 2697 MHz AIN = –1 dBFS –59
AIN = –3 dBFS –64
AIN = –12 dBFS –80
fIN = 3497 MHz AIN = –1 dBFS –57
AIN = –3 dBFS –61
AIN = –12 dBFS –78
HD3 3rd-order harmonic distortion fIN = 97 MHz AIN = –1 dBFS –67 dBFS
AIN = –3 dBFS –71
AIN = –12 dBFS –83
AIN = –3 dBFS, VFS = 1.0 VPP –71
fIN = 497 MHz AIN = –1 dBFS –68
AIN = –3 dBFS –79
AIN = –12 dBFS –79
fIN = 997 MHz AIN = –1 dBFS –74 –55
AIN = –3 dBFS –75
AIN = –12 dBFS –82
AIN = –3 dBFS, VFS = 1.0 VPP –74
fIN = 1797 MHz AIN = –1 dBFS –61
AIN = –3 dBFS –69
AIN = –12 dBFS –78
fIN = 2697 MHz AIN = –1 dBFS –54
AIN = –3 dBFS –60
AIN = –12 dBFS –81
fIN = 3497 MHz AIN = –1 dBFS –49
AIN = –3 dBFS –56
AIN = –12 dBFS –76
SPUR Worst spur, excluding DC, HD2, HD3 fIN = 97 MHz AIN = –1 dBFS –77 dBFS
AIN = –3 dBFS –77
AIN = –12 dBFS –79
AIN = –3 dBFS, VFS = 1.0 VPP –79
fIN = 497 MHz AIN = –1 dBFS –75
AIN = –3 dBFS –80
AIN = –12 dBFS –80
fIN = 997 MHz AIN = –1 dBFS –76 –65
AIN = –3 dBFS –79
AIN = –12 dBFS –80
AIN = –3 dBFS, VFS = 1.0 VPP –77
fIN = 1797 MHz AIN = –1 dBFS –75
AIN = –3 dBFS –78
AIN = –12 dBFS –75
fIN = 2697 MHz AIN = –1 dBFS –75
AIN = –3 dBFS –77
AIN = –12 dBFS –81
fIN = 3497 MHz AIN = –1 dBFS –73
AIN = –3 dBFS –76
AIN = –12 dBFS –79
IMD3 3rd-order intermodulation distortion f1 = 93 MHz,
f2 = 103 MHz		 AIN = –7 dBFS per tone –78 dBFS
AIN = –9 dBFS per tone –85
AIN = –18 dBFS per tone –89
AIN = –9 dBFS per tone, VFS = 1.0 VPP –83
f1 = 493 MHz,
f2 = 503 MHz		 AIN = –7 dBFS per tone –82
AIN = –9 dBFS per tone –85
AIN = –18 dBFS per tone –84
f1 = 993 MHz,
f2 = 1003 MHz		 AIN = –7 dBFS per tone –75
AIN = –9 dBFS per tone –80
AIN = –18 dBFS per tone –84
AIN = –9 dBFS per tone, VFS = 1.0 VPP –79
f1 = 1793 MHz,
f2 = 1803 MHz		 AIN = –7 dBFS per tone –66
AIN = –9 dBFS per tone –73
AIN = –18 dBFS per tone –89
f1 = 2693 MHz,
f2 = 2703 MHz		 AIN = –7 dBFS per tone –56
AIN = –9 dBFS per tone –63
AIN = –18 dBFS per tone –83
f1 = 3493 MHz,
f2= 3503 MHz		 AIN = –7 dBFS per tone –50
AIN = –9 dBFS per tone –57
AIN = –18 dBFS per tone –90
(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input bandwidth.