SLVSDR2B November 2018 – March 2021 ADC12DJ3200QML-SP
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | SUBGROUP(1) | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
DC ACCURACY | |||||||
Resolution | Resolution with no missing codes | 12 | Bits | ||||
DNL | Differential nonlinearity | Maximum positive excursion from ideal step size | 0.4 | LSB | |||
Maximum negative excursion from ideal step size | –0.3 | LSB | |||||
INL | Integral nonlinearity | Maximum positive excursion from ideal transfer function | 3 | LSB | |||
Maximum negative excursion from ideal transfer function | –2 | LSB | |||||
ANALOG INPUTS (INA+, INA–, INB+, INB–) | |||||||
VOFF | Offset error | CAL_OS = 0 | ±2.0 | mV | |||
CAL_OS = 1 | ±0.5 | mV | |||||
VOFF_ADJ | Input offset voltage adjustment range | Available offset correction range (see CAL_OS bit in the CAL_CFG0 register or the OADJ_A_FG0_VINA register) | ±55 | mV | |||
VOFF_DRIFT | Offset drift | Foreground calibration at nominal temperature only | 23 | µV/°C | |||
Foreground calibration at each temperature | 0 | ||||||
VIN_FSR | Analog differential input full-scale range | Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) | [1, 2, 3] | 750 | 810 | 850 | mVPP |
Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) | 1050 | ||||||
Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000) | 490 | ||||||
VIN_FSR_DRIFT | Analog differential input full-scale range drift | Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by 50-Ω source, includes effect of RIN drift | –0.01 | %/°C | |||
Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by 50-Ω source, includes effect of RIN drift | –0.022 | ||||||
VIN_FSR_MATCH | Analog differential input full-scale range matching | Matching between INA± and INB±, default setting, dual-channel mode | 1% | ||||
RIN | Single-ended input resistance to AGND | Each input pin is terminated to AGND, measured at TA = 25°C | [1] | 48 | 50 | 52 | Ω |
RIN_TEMPCO | Input termination linear temperature coefficient | 14.7 | mΩ/°C | ||||
CIN | Single-ended input capacitance | Single-channel mode at DC | 0.4 | pF | |||
Dual-channel mode at DC | 0.4 | ||||||
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–) | |||||||
ΔVBE | Temperature diode voltage slope | Forced forward current of 100 µA; offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each device; perform offset measurement with the device unpowered or with the PD pin asserted to minimize device self-heating; only assert the PD pin long enough to take the offset measurement | –1.6 | mV/°C | |||
BAND-GAP VOLTAGE OUTPUT (BG) | |||||||
VBG | Reference output voltage | IL ≤ 100 µA | 1.1 | V | |||
VBG_DRIFT | Reference output temperature drift | IL ≤ 100 µA | –102 | µV/°C | |||
CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–) | |||||||
ZT | Internal termination | Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 | 100 | Ω | |||
Single-ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 | 50 | ||||||
VCM | Input common-mode voltage, self-biased | Self-biasing common-mode voltage for CLK± when AC-coupled (DEVCLK_LVPECL_EN must be set to 0) | 0.3 | V | |||
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1) | 0.3 | ||||||
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0) | VA11 | ||||||
CL_DIFF | Differential input capacitance | Between positive and negative differential input pins | 0.1 | pF | |||
CL_SE | Single-ended input capacitance | Each input to ground | 0.5 | pF | |||
SERDES OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–) | |||||||
VOD | Differential output voltage, peak-to-peak | 100-Ω load | [1, 2, 3] | 550 | 600 | 650 | mVPP-DIFF |
VCM | Output common-mode voltage | AC-coupled | VD11 / 2 | V | |||
ZDIFF | Differential output impedance | 100 | Ω | ||||
CMOS INTERFACE (SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE) | |||||||
IIH | High-level input current | [1, 2, 3] | 40 | µA | |||
IIL | Low-level input current | [1, 2, 3] | –40 | µA | |||
CI | Input capacitance | 2 | pF | ||||
VOH | High-level output voltage | ILOAD = –400 µA | [1, 2, 3] | 1.65 | V | ||
VOL | Low-level output voltage | ILOAD = 400 µA | [1, 2, 3] | 150 | mV |