SBAS670B July   2014  – April 2017 ADC3441 , ADC3442 , ADC3443 , ADC3444

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADC3441, ADC3442
    7. 7.7  Electrical Characteristics: ADC3443, ADC3444
    8. 7.8  AC Performance: ADC3441
    9. 7.9  AC Performance: ADC3442
    10. 7.10 AC Performance: ADC3443
    11. 7.11 AC Performance: ADC3444
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements: General
    14. 7.14 Timing Requirements: LVDS Output
    15. 7.15 Typical Characteristics: ADC3441
    16. 7.16 Typical Characteristics: ADC3442
    17. 7.17 Typical Characteristics: ADC3443
    18. 7.18 Typical Characteristics: ADC3444
    19. 7.19 Typical Characteristics: Common
    20. 7.20 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 Using the SYSREF Input
        2. 9.3.2.2 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 14x Serialization
        2. 9.3.3.2 Two-Wire Interface: 7x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
      4. 9.4.4 Internal Dither Algorithm
      5. 9.4.5 Summary of Performance Mode Registers
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 ADC3441 Power-Up Requirements
    6. 9.6 Register Maps
      1. 9.6.1 Serial Register Description
        1. 9.6.1.1  Register 01h (address = 01h)
        2. 9.6.1.2  Register 03h (address = 03h)
        3. 9.6.1.3  Register 04h (address = 04h)
        4. 9.6.1.4  Register 05h (address = 05h)
        5. 9.6.1.5  Register 06h (address = 06h)
        6. 9.6.1.6  Register 07h (address = 07h)
        7. 9.6.1.7  Register 09h (address = 09h)
        8. 9.6.1.8  Register 0Ah (address = 0Ah)
        9. 9.6.1.9  Register 0Bh (address = 0Bh)
        10. 9.6.1.10 Register 13h (address = 13h)
        11. 9.6.1.11 Register 0Eh (address = 0Eh)
        12. 9.6.1.12 Register 0Fh (address = 0Fh)
        13. 9.6.1.13 Register 15h (address = 15h)
        14. 9.6.1.14 Register 25h (address = 25h)
        15. 9.6.1.15 Register 27h (address = 27h)
        16. 9.6.1.16 Register 11Dh (address = 11Dh)
        17. 9.6.1.17 Register 122h (address = 122h)
        18. 9.6.1.18 Register 134h (address = 134h)
        19. 9.6.1.19 Register 139h (address = 139h)
        20. 9.6.1.20 Register 21Dh (address = 21Dh)
        21. 9.6.1.21 Register 222h (address = 222h)
        22. 9.6.1.22 Register 234h (address = 234h)
        23. 9.6.1.23 Register 239h (address = 239h)
        24. 9.6.1.24 Register 308h (address = 308h)
        25. 9.6.1.25 Register 41Dh (address = 41Dh)
        26. 9.6.1.26 Register 422h (address = 422h)
        27. 9.6.1.27 Register 434h (address = 434h)
        28. 9.6.1.28 Register 439h (address = 439h)
        29. 9.6.1.29 Register 51Dh (address = 51Dh)
        30. 9.6.1.30 Register 522h (address = 522h)
        31. 9.6.1.31 Register 534h (address = 534h)
        32. 9.6.1.32 Register 539h (address = 539h)
        33. 9.6.1.33 Register 608h (address = 608h)
        34. 9.6.1.34 Register 70Ah (address = 70Ah)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) may be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 195 and Figure 196 show the impedance (Zin = Rin || Cin) across the ADC input pins.

ADC3441 ADC3442 ADC3443 ADC3444 D024_BAS671.gif Figure 195. Differential Input Resistance, RIN
ADC3441 ADC3442 ADC3443 ADC3444 D025_BAS671.gif Figure 196. Differential Input Capacitance, CIN

10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

ADC3441 ADC3442 ADC3443 ADC3444 Drv_Crct_Lw_Inpt_Freq_BAS663.gif Figure 197. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin may be kept to damp out ringing caused by package parasitic. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.

10.2.1.2 Detailed Design Procedure

A typical application involving using two back-to-back coupled transformers is shown in Figure 197. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used with the series inductor (39 nH), this combination helps absorb the sampling glitches. To improve phase and amplitude balance of first transformer, the termination resistors can be split between two transformers. For example, 25-Ω to 25-Ω termination across the secondary winding of the second transformer can be changed to 50-Ω to 50-Ω termination and another 50-Ω to 50-Ω resistor can be placed inside the dashed box between the transformers in Figure 197.

10.2.1.3 Application Curve

Figure 198 shows the performance obtained by using the circuit shown in Figure 197.

ADC3441 ADC3442 ADC3443 ADC3444 D101_SBAS670.gif
SFDR = 95 dBc, SNR = 72.7 dBFS, SINAD = 72.6 dBFS,
THD = 100 dBc, HD2 = 95 dBc, HD3 = 96 dBc
Figure 198. FFT for 10-MHz Input Signal
(Chopper On, Dither On)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

ADC3441 ADC3442 ADC3443 ADC3444 Drv_Crct_Md_Inpt_Freq_BAS663.gif Figure 199. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit may be used to optimize performance, as shown in Figure 199.

10.2.2.3 Application Curve

Figure 200 shows the performance obtained by using the circuit shown in Figure 199.

ADC3441 ADC3442 ADC3443 ADC3444 D105_SBAS670.gif
SFDR = 86 dBc, SNR = 71.7 dBFS, SINAD = 71.6 dBFS,
THD = 93 dBc, HD2 = 86 dBc, HD3 = 99 dBc
Figure 200. FFT for 170-MHz Input Signal (Chopper Off, Dither On)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

ADC3441 ADC3442 ADC3443 ADC3444 Drv_Crct_Hg_Inpt_Freq_BAS663.gif Figure 201. Driving Circuit for High Input Frequencies (fIN > 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω may be used as shown in Figure 201.

10.2.3.3 Application Curve

Figure 202 shows the performance obtained by using the circuit shown in Figure 201.

ADC3441 ADC3442 ADC3443 ADC3444 D109_SBAS670.gif
SFDR = 72 dBc, SNR = 68.2 dBFS, SINAD = 67.3 dBFS,
THD = 74 dBc, HD2 = 72 dBc, HD3 = 79 dBc
Figure 202. FFT for 450-MHz Input Signal (Chopper Off, Dither On)