SBAS669A May   2014  – January 2015 ADC34J22 , ADC34J23 , ADC34J24 , ADC34J25

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Summary of Special Mode Registers
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics: ADC34J24, ADC34J25
    7. 7.7  Electrical Characteristics: ADC34J22, ADC34J23
    8. 7.8  Electrical Characteristics: General
    9. 7.9  AC Performance: ADC34J25
    10. 7.10 AC Performance: ADC34J24
    11. 7.11 AC Performance: ADC34J23
    12. 7.12 AC Performance: ADC34J22
    13. 7.13 Digital Characteristics
    14. 7.14 Timing Characteristics
    15. 7.15 Typical Characteristics: ADC34J25
    16. 7.16 Typical Characteristics: ADC34J24
    17. 7.17 Typical Characteristics: ADC34J23
    18. 7.18 Typical Characteristics: ADC34J22
    19. 7.19 Typical Characteristics: Common Plots
    20. 7.20 Typical Characteristics: Contour Plots
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
        2. 9.3.2.2 Input Clock Divider
      3. 9.3.3 Power-Down Control
      4. 9.3.4 Internal Dither Algorithm
      5. 9.3.5 JESD204B Interface
        1. 9.3.5.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.3.5.2 JESD204B Test Patterns
        3. 9.3.5.3 JESD204B Frame Assembly
        4. 9.3.5.4 Digital Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Gain
      2. 9.4.2 Overrange Indication
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
      3. 9.5.3 Start-Up Sequence
    6. 9.6 Register Map
      1. 9.6.1 Serial Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage range, AVDD –0.3 2.1 V
Supply voltage range, DVDD –0.3 2.1 V
Voltage applied to input pins: INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM –0.3 Minimum
(AVDD + 0.3, 2.1)		 V
CLKP, CLKM(2) –0.3 Minimum
(AVDD + 0.3, 2.1)		 V
SYSREFP, SYSREFM, SYNCP~, SYNCM~ –0.3 Minimum
(AVDD + 0.3, 2.1)		 V
SCLK, SEN, SDATA, RESET, PDN –0.3 3.6 V
Temperature Operating free-air, TA –40 85 °C
Operating junction, TJ 125 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|). This configuration prevents the ESD protection diodes at the clock input pins from turning on.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions(2)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage range 1.7 1.8 1.9 V
DVDD Digital supply voltage range 1.7 1.8 1.9 V
ANALOG INPUT
VID Differential input voltage For input frequencies < 450 MHz 2 VPP
For input frequencies < 600 MHz 1 VPP
VIC Input common-mode voltage VCM ± 0.025 V
CLOCK INPUT
Input clock frequency Sampling clock frequency 25 160(1) MSPS
Input clock amplitude (differential) Sine wave, ac-coupled 0.2 1.5 V
LPECL, ac-coupled 1.6 V
LVDS, ac-coupled 0.7 V
Input clock duty cycle 35 50 65 %
Input clock common-mode voltage 0.95 V
DIGITAL OUTPUTS
CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF
RLOAD Single-ended load resistance 100 Ω
(1) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 640 MSPS.
(2) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section.

7.4 Summary of Special Mode Registers

Table 1 lists the location, value, and functions of special mode registers in the device.

Table 1. Special Modes Summary

MODE LOCATION VALUE AND FUNCTION
Dither mode DIS DITH CHA 01h [7:6], 134h[5,3] Creates a noise floor cleaner and improves SFDR; see the Internal Dither Algorithm section.
0000 = Dither disabled
1111 = Dither enabled
DIS DITH CHB 01h [5:4], 434h[5,3]
DIS DITH CHC 01h [3:2], 534h[5,3]
DIS DITH CHD 01h [1:0], 234h[5,3]
Special mode 1 SPECIAL MODE 1 CHA 06h[4:2] Use for better HD3.
000 = Default after reset
010 = Use for frequency < 120 MHz
111 = Use for frequency > 120 MHz
SPECIAL MODE 1 CHB 07h[4:2]
SPECIAL MODE 1 CHC 08h[4:2]
SPECIAL MODE 1 CHD 09h[4:2]
Special mode 2 SPECIAL MODE 2 CHA 122h[1:0] Helps improve HD2.
00 = Default after reset
11 = Improves HD2
SPECIAL MODE 2 CHB 422h[1:0]
SPECIAL MODE 2 CHC 522h[1:0]
SPECIAL MODE 2 CHD 222h[1:0]

7.5 Thermal Information

THERMAL METRIC(1) ADC34J2x UNIT
RGZ (VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 25.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.9
RθJB Junction-to-board thermal resistance 3.0
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 3
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.6 Electrical Characteristics: ADC34J24, ADC34J25

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC34J24 ADC34J25 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 125 160 MSPS
Resolution 12 12 Bits
1.8-V analog supply (AVDD) current 318 490 354 490 mA
1.8-V digital supply current 79 150 97 150 mA
Total power dissipation 715 1010 812 1010 mW
Global power-down dissipation 22 22 mW
Wake-up time from global power-down 85 100 85 100 µs
Standby power-down dissipation 177 185 mW
Wake-up time from standby power-down 35 300 35 300 µs

7.7 Electrical Characteristics: ADC34J22, ADC34J23

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC34J22 ADC34J23 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 50 80 MSPS
Resolution 12 12 Bits
1.8-V analog supply current 233 490 269 490 mA
1.8-V digital supply current 39 150 56 150 mA
Total power dissipation 491 1010 584 1010 mW
Global power-down dissipation 22 22 mW
Wake-up time from global power-down 85 100 85 100 µs
Standby power-down dissipation 155 166 mW
Wake-up time from standby power-down 35 300 35 300 µs

7.8 Electrical Characteristics: General

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Differential input full-scale 2.0 VPP
ri Input resistance Differential at dc 6.5 kΩ
ci Input capacitance Differential at dc 5.2 pF
VOC(VCM) VCM common-mode voltage output 0.95 V
VCM output current capability 10 mA
Input common-mode current Per analog input pin 1.5 µA/MSPS
Analog input bandwidth (3 dB) 50-Ω differential source driving 50-Ω termination across INP and INM 450 MHz
DC ACCURACY
EO Offset error –20 20 mV
EG(REF) Gain error as a result of internal reference inaccuracy alone –3 3 %FS
EG(CHAN) Gain error of channel alone ±1 %FS
CHANNEL-TO-CHANNEL ISOLATION
Crosstalk(1) fIN = 10 MHz Near channel 105 dB
Far channel 105 dB
fIN = 100 MHz Near channel 95 dB
Far channel 105 dB
fIN = 200 MHz Near channel 94 dB
Far channel 105 dB
fIN = 230 MHz Near channel 93 dB
Far channel 105 dB
fIN = 300 MHz Near channel 85 dB
Far channel 105 dB
(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on victim channel.

7.9 AC Performance: ADC34J25

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC34J25 (fS = 160 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 70.2 70.4 dBFS
fIN = 70 MHz 68.5 69.6 69.9
fIN = 100 MHz 69.3 69.6
fIN = 170 MHz 68.4 68.9
fIN = 230 MHz 67.5 68.1
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 149.2 149.4 dBFS/Hz
fIN = 70 MHz 147.5 148.6 148.9
fIN = 100 MHz 148.3 148.6
fIN = 170 MHz 147.4 147.9
fIN = 230 MHz 146.5 147.1
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 70.1 70.3 dBFS
fIN = 70 MHz 67.6 69.5 69.7
fIN = 100 MHz 69.2 69.4
fIN = 170 MHz 68.2 68.6
fIN = 230 MHz 67.2 67.5
ENOB Effective number of bits fIN = 10 MHz 11.4 11.4 Bits
fIN = 70 MHz 10.9 11.3 11.3
fIN = 100 MHz 11.2 11.3
fIN = 170 MHz 11.1 11.1
fIN = 230 MHz 10.9 10.9
SFDR Spurious-free dynamic range fIN = 10 MHz 85 86 dBc
fIN = 70 MHz 81 86 85
fIN = 100 MHz 86 87
fIN = 170 MHz 85 84
fIN = 230 MHz 81 80
HD2 Second harmonic distortion fIN = 10 MHz 91 92 dBc
fIN = 70 MHz 81 94 93
fIN = 100 MHz 93 91
fIN = 170 MHz 83 83
fIN = 230 MHz 81 79
HD3 Third harmonic distortion fIN = 10 MHz 85 86 dBc
fIN = 70 MHz 81 85 85
fIN = 100 MHz 86 87
fIN = 170 MHz 93 87
fIN = 230 MHz 85 82
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 98 94 dBc
fIN = 70 MHz 87 97 94
fIN = 100 MHz 96 93
fIN = 170 MHz 92 92
fIN = 230 MHz 90 89
THD Total harmonic distortion fIN = 10 MHz 84 83 dBc
fIN = 70 MHz 76.5 84 83
fIN = 100 MHz 84 84
fIN = 170 MHz 82 80
fIN = 230 MHz 78 76
IMD3 Third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 92 92 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 87 87

7.10 AC Performance: ADC34J24

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC34J24 (fS = 125 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 70.3 70.6 dBFS
fIN = 70 MHz 68.8 70.1 70.4
fIN = 100 MHz 69.9 70.2
fIN = 170 MHz 69.1 69.7
fIN = 230 MHz 68.6 69.1
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 148.3 148.6 dBFS/Hz
fIN = 70 MHz 146.8 148.1 148.4
fIN = 100 MHz 147.9 148.2
fIN = 170 MHz 147.1 147.7
fIN = 230 MHz 146.6 147.1
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 70.3 70.5 dBFS
fIN = 70 MHz 67.6 70 70.3
fIN = 100 MHz 69.8 70.1
fIN = 170 MHz 68.9 69.3
fIN = 230 MHz 68.4 68.8
ENOB Effective number of bits fIN = 10 MHz 11.4 11.4 Bits
fIN = 70 MHz 10.9 11.4 11.4
fIN = 100 MHz 11.3 11.4
fIN = 170 MHz 11.2 11.3
fIN = 230 MHz 11.1 11.1
SFDR Spurious-free dynamic range fIN = 10 MHz 94 92 dBc
fIN = 70 MHz 81 93 91
fIN = 100 MHz 93 92
fIN = 170 MHz 85 83
fIN = 230 MHz 83 82
HD2 Second harmonic distortion fIN = 10 MHz 93 93 dBc
fIN = 70 MHz 81 94 94
fIN = 100 MHz 92 92
fIN = 170 MHz 83 83
fIN = 230 MHz 82 82
HD3 Third harmonic distortion fIN = 10 MHz 96 93 dBc
fIN = 70 MHz 83 94 91
fIN = 100 MHz 95 93
fIN = 170 MHz 88 86
fIN = 230 MHz 87 88
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 95 dBc
fIN = 70 MHz 87 98 95
fIN = 100 MHz 97 95
fIN = 170 MHz 97 92
fIN = 230 MHz 95 92
THD Total harmonic distortion fIN = 10 MHz 89 87 dBc
fIN = 70 MHz 76.5 89 87
fIN = 100 MHz 89 87
fIN = 170 MHz 82 80
fIN = 230 MHz 81 80
IMD3 Third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 97 97 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 89 89

7.11 AC Performance: ADC34J23

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC34J23 (fS = 80 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 70.2 70.4 dBFS
fIN = 70 MHz 68.7 70 70.3
fIN = 100 MHz 69.9 70.1
fIN = 170 MHz 69.3 69.6
fIN = 230 MHz 68.7 68.9
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 146.1 146.3 dBFS/Hz
fIN = 70 MHz 144.8 145.9 146.2
fIN = 100 MHz 145.8 146.0
fIN = 170 MHz 145.2 145.5
fIN = 230 MHz 144.6 144.8
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 70.2 70.3 dBFS
fIN = 70 MHz 67.6 70 70.2
fIN = 100 MHz 69.8 69.9
fIN = 170 MHz 69.1 69.3
fIN = 230 MHz 68.2 68.4
ENOB Effective number of bits fIN = 10 MHz 11.4 11.4 Bits
fIN = 70 MHz 10.9 11.4 11.4
fIN = 100 MHz 11.3 11.3
fIN = 170 MHz 11.2 11.3
fIN = 230 MHz 11.1 11.1
SFDR Spurious-free dynamic range fIN= 10 MHz 95 91 dBc
fIN = 70 MHz 82 95 90
fIN = 100 MHz 90 89
fIN = 170 MHz 87 84
fIN = 230 MHz 80 80
HD2 Second harmonic distortion fIN = 10 MHz 95 95 dBc
fIN = 70 MHz 82 95 94
fIN = 100 MHz 91 92
fIN = 170 MHz 83 83
fIN = 230 MHz 81 82
HD3 Third harmonic distortion fIN = 10 MHz 99 94 dBc
fIN = 70 MHz 83 101 94
fIN = 100 MHz 91 90
fIN = 170 MHz 92 90
fIN = 230 MHz 80 80
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 98 92 dBc
fIN = 70 MHz 87 98 92
fIN = 100 MHz 97 91
fIN = 170 MHz 96 91
fIN = 230 MHz 93 91
THD Total harmonic distortion fIN = 10 MHz 91 86 dBc
fIN = 70 MHz 76.5 91 86
fIN = 100 MHz 87 84
fIN = 170 MHz 82 81
fIN = 230 MHz 77 77
IMD3 Third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 95 95 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 88 88

7.12 AC Performance: ADC34J22

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC34J22 (fS = 50 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 69.3 70.2 70.5 dBFS
fIN = 70 MHz 70 70.3
fIN = 100 MHz 69.9 70.2
fIN = 170 MHz 69.3 69.5
fIN = 230 MHz 67.9 68
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 143.3 144.2 144.5 dBFS/Hz
fIN = 70 MHz 144 144.3
fIN = 100 MHz 143.9 144.2
fIN = 170 MHz 143.3 143.5
fIN = 230 MHz 141.9 142
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 67.6 70.2 70.4 dBFS
fIN = 70 MHz 69.9 70.1
fIN = 100 MHz 69.8 70
fIN = 170 MHz 69.1 69.3
fIN = 230 MHz 67.5 67.6
ENOB Effective number of bits fIN = 10 MHz 10.9 11.4 11.4 Bits
fIN = 70 MHz 11.3 11.3
fIN = 100 MHz 11.3 11.3
fIN = 170 MHz 11.2 11.2
fIN = 230 MHz 10.9 10.9
SFDR Spurious-free dynamic range fIN = 10 MHz 84.5 95 91 dBc
fIN = 70 MHz 93 90
fIN = 100 MHz 90 89
fIN = 170 MHz 85 84
fIN = 230 MHz 80 80
HD2 Second harmonic distortion fIN = 10 MHz 84.5 94 93 dBc
fIN = 70 MHz 93 93
fIN = 100 MHz 90 90
fIN = 170 MHz 83 83
fIN = 230 MHz 81 81
HD3 Third harmonic distortion fIN = 10 MHz 84.5 102 96 dBc
fIN = 70 MHz 94 92
fIN = 100 MHz 90 89
fIN = 170 MHz 91 90
fIN = 230 MHz 80 80
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 87 98 92 dBc
fIN = 70 MHz 97 92
fIN = 100 MHz 96 92
fIN = 170 MHz 95 91
fIN = 230 MHz 93 91
THD Total harmonic distortion fIN = 10 MHz 76.5 91 86 dBc
fIN = 70 MHz 89 85
fIN = 100 MHz 86 84
fIN = 170 MHz 82 81
fIN = 230 MHz 77 77
IMD3 Third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 93 93 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 86 86

7.13 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN)(1)
VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels 1.2 V
VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels 0.4 V
IIH High-level input current SEN 0 µA
RESET, SCLK, SDATA, PDN 10 µA
IIL Low-level input current SEN 10 µA
RESET, SCLK, SDATA, PDN 0 µA
DIGITAL INPUTS (SYNCP~, SYNCM~, SYSREFP, SYSREFM)
VIH High-level input voltage 1.3 V
VIL Low-level input voltage 0.5 V
V(CM_DIG) Common-mode voltage for SYNC~ and SYSREF 0.9 V
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB, OVRC, OVRD)
VOH High-level output voltage DVDD – 0.1 DVDD V
VOL Low-level output voltage 0.1 V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2)
VOH High-level output voltage DVDD V
VOL Low-level output voltage DVDD – 0.4 V
VOD Output differential voltage 0.4 V
VOC Output common-mode voltage DVDD – 0.2 V
Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA
zos Single-ended output impedance 50 Ω
Output capacitance Output capacitance inside the device,
from either output to ground		 2 pF
(1) RESET, SCLK, SDATA, and PDN pins have 150-kΩ (typical) internal pull-down resistor to ground, while SEN pin has 150-kΩ (typical) pull-up resistor to AVDD.
(2) 50-Ω, single-ended external termination to 1.8 V.

7.14 Timing Characteristics

Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. See Figure 143.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAMPLE TIMING CHARACTERISTICS
Aperture delay 0.85 1.25 1.65 ns
Aperture delay matching Between two channels on the same device ±70 ps
Between two devices at the same temperature and supply voltage ±150 ps
Aperture jitter 200 fS rms
Wake-up time Time to valid data after coming out of STANDBY mode 35 100 µs
Time to valid data after coming out of global power-down 85 300 µs
tSU_SYNC~ Setup time for SYNC~ Referenced to input clock rising edge 1 ns
tH_SYNC~ Hold time for SYNC~ Referenced to input clock rising edge 100 ps
tSU_SYSREF Setup time for SYSREF Referenced to input clock rising edge 1 ns
tH_SYSREF Hold time for SYSREF Referenced to input clock rising edge 100 ps
CML OUTPUT TIMING CHARACTERISTICS
Unit interval 312.5 1667 ps
Serial output data rate 3.2 Gbps
Total jitter 3.125 Gbps (20x mode, fS = 156.25 MSPS) 0.3 P-PUI
tR, tF Data rise time,
data fall time		 Rise and fall times measured from 20% to 80%,
differential output waveform,
600 Mbps ≤ bit rate ≤ 3.125 Gbps		 105 ps

Table 2. Latency in Different Modes(1)(2)

MODE PARAMETER LATENCY (N Cycles) TYPICAL DATA DELAY (tD, ns)
20x ADC latency 17 0.29 × tS + 3
Normal OVR latency 9 0.5 × tS + 2
Fast OVR latency 7 0.5 × tS + 2
From SYNC~ falling edge to CGS phase(3) 15 0.3 × tS + 4
From SYNC~ rising edge to ILA sequence(4) 17 0.3 × tS + 4
40x ADC latency 16 0.85 × tS + 3.9
Normal OVR latency 9 0.5 × tS + 2
Fast OVR latency 7 0.5 × tS + 2
From SYNC~ falling edge to CGS phase(3) 14 0.9 × tS + 4
From SYNC~ rising edge to ILA sequence(4) 12 0.9 × tS + 4
(1) Overall latency = latency + tD.
(2) tS is the time period of the ADC conversion clock.
(3) Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15 clock cycles in 20x mode.
(4) Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and 11 clock cycles in 20x mode.

7.15 Typical Characteristics: ADC34J25

Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.
C001_BAS669.png
fS = 160 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz, SFDR = 84 dBc
Figure 1. FFT for 10-MHz Input Signal (Dither On)
C003_BAS669.png
fS = 160 MSPS, SNR = 69.7 dBFS, fIN = 70 MHz, SFDR = 86 dBc
Figure 3. FFT for 70-MHz Input Signal (Dither On)
C005_BAS669.png
fS = 160 MSPS, SNR = 67.9 dBFS, fIN = 170 MHz,
SFDR = 84.1 dBc
Figure 5. FFT for 170-MHz Input Signal (Dither On)
C007_BAS669.png
fS = 160 MSPS, SNR = 67.0 dBFS, fIN = 270 MHz,
SFDR = 76.2 dBc
Figure 7. FFT for 270-MHz Input Signal (Dither On)
C009_BAS669.png
fS = 160 MSPS, SNR = 62.9 dBFS, fIN = 450 MHz,
SFDR = 67.8 dBc
Figure 9. FFT for 450-MHz Input Signal (Dither On)
C011_BAS669.png
fS = 160 MSPS, IMD = 92 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 96 dBFS
Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
C013_BAS669.png
fS = 160 MSPS, IMD = 87 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 90 dBFS
Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
C015_BAS669.png
Figure 15. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
C017_BAS669.png
Figure 17. Signal-to-Noise Ratio vs Input Frequency
C019_BAS669.png
Figure 19. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
C021_BAS669.gif
Figure 21. Performance vs Input Amplitude
(30 MHz)
C023_BAS669.gif
Figure 23. Performance vs Input Common-Mode Voltage
(30 MHz)
C025_BAS669.gif
Figure 25. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
C027_SBAS669.gif
Figure 27. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
C029_BAS669.png
Figure 29. Performance vs Clock Amplitude
(40 MHz)
C031_BAS669.png
Figure 31. Performance vs Clock Duty Cycle
(40 MHz)
C033_BAS669.png
RMS noise = 1.3 LSBs
Figure 33. Idle Channel Histogram
C002_BAS669.png
fS = 160 MSPS, SNR = 70.7 dBFS, fIN = 10 MHz,
SFDR = 81.1 dBc
Figure 2. FFT for 10-MHz Input Signal (Dither Off)
C004_BAS669.png
fS = 160 MSPS, SNR = 70.1 dBFS, fIN = 70 MHz,
SFDR = 87.5 dBc
Figure 4. FFT for 70-MHz Input Signal (Dither Off)
C006_BAS669.png
fS = 160 MSPS, SNR = 68.1 dBFS, fIN = 70 MHz,
SFDR = 82.7 dBc
Figure 6. FFT for 170-MHz Input Signal (Dither Off)
C008_BAS669.png
fS = 160 MSPS, SNR = 67.5 dBFS, fIN = 270 MHz,
SFDR = 75.9 dBc
Figure 8. FFT for 270-MHz Input Signal (Dither Off)
C010_BAS669.png
fS = 160 MSPS, SNR = 63.6 dBFS, fIN = 450 MHz,
SFDR = 67.6 dBc
Figure 10. FFT for 450-MHz Input Signal (Dither Off)
C012_BAS669.png
fS = 160 MSPS, IMD = 98 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 102 dBFS
Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
C014_BAS669.png
fS = 160 MSPS, IMD = 98 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 102 dBFS
Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
C016_BAS669.png
Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
C018_BAS669.png
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
C020_BAS669.png
Figure 20. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
C022_BAS669.gif
Figure 22. Performance vs Input Amplitude
(170 MHz)
C024_BAS669.gif
Figure 24. Performance vs Input Common-Mode Voltage (170 MHz)
C026_SBAS669.gif
Figure 26. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
C028_BAS669.gif
Figure 28. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
C030_BAS669.png
Figure 30. Performance vs Clock Amplitude
(150 MHz)
C032_BAS669.png
Figure 32. Performance vs Clock Duty Cycle
(150 MHz)

7.16 Typical Characteristics: ADC34J24

Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
C101_BAS669.png
fS = 125 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz,
SFDR = 91.3 dBc
Figure 34. FFT for 10-MHz Input Signal (Dither On)
C103_BAS669.png
fS = 125 MSPS, SNR = 70 dBFS, fIN = 70 MHz, SFDR = 93.5 dBc
Figure 36. FFT for 70-MHz Input Signal (Dither On)
C105_BAS669.png
fS = 125 MSPS, SNR = 69 dBFS, fIN = 170 MHz,
SFDR = 85.9 dBc
Figure 38. FFT for 170-MHz Input Signal (Dither On)
C107_BAS669.png
fS = 125 MSPS, SNR = 68.4 dBFS, fIN = 270 MHz,
SFDR = 79.8 dBc
Figure 40. FFT for 270-MHz Input Signal (Dither On)
C109_BAS669.png
fS = 125 MSPS, SNR = 65.2 dBFS, fIN = 450 MHz,
SFDR = 62.9 dBc
Figure 42. FFT for 450-MHz Input Signal (Dither On)
C111_BAS669.png
fS = 125 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 97 dBFS
Figure 44. FFT for Two-Tone Input Signal
(–7dBFS at 46 MHz and 50 MHz)
C113_BAS669.png
fS = 125 MSPS, IMD = 89 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 92 dBFS
Figure 46. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
C115_BAS669.png
Figure 48. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
C117_BAS669.png
Figure 50. Signal-to-Noise Ratio vs Input Frequency
C119_BAS669.gif
Figure 52. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
C121_BAS669.gif
Figure 54. Performance vs Input Amplitude
(30 MHz)
C123_BAS669.png
Figure 56. Performance vs Input Common-Mode Voltage
(30 MHz)
C125_BAS669.gif
Figure 58. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
C127_BAS669.gif
Figure 60. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
C129_BAS669.png
Figure 62. Performance vs Clock Amplitude
(40 MHz)
C131_BAS669.png
Figure 64. Performance vs Clock Duty Cycle
(40 MHz)
C133_BAS669.png
RMS noise = 1.4 LSBs
Figure 66. Idle Channel Histogram
C102_BAS669.png
fS = 125 MSPS, SNR = 70.5 dBFS, fIN = 10 MHz,
SFDR = 90.9 dBc
Figure 35. FFT for 10-MHz Input Signal (Dither Off)
C104_BAS669.png
fS = 125 MSPS, SNR = 70.3 dBFS, fIN = 70 MHz,
SFDR = 94.3 dBc
Figure 37. FFT for 70-MHz Input Signal (Dither Off)
C106_BAS669.png
fS = 125 MSPS, SNR = 69.6 dBFS, fIN = 70 MHz,
SFDR = 86.5 dBc
Figure 39. FFT for 170-MHz Input Signal (Dither Off)
C108_BAS669.png
fS = 125 MSPS, SNR = 68.8 dBFS, fIN = 270 MHz,
SFDR = 79.6 dBc
Figure 41. FFT for 270-MHz Input Signal (Dither Off)
C110_BAS669.png
fS = 125 MSPS, SNR = 66.1 dBFS, fIN = 450 MHz,
SFDR = 63.1 dBc
Figure 43. FFT for 450-MHz Input Signal (Dither Off)
C112_BAS669.png
fS = 125 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 106 dBFS
Figure 45. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
C114_BAS669.png
fS = 125 MSPS, IMD = 99 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 103 dBFS
Figure 47. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
C116_BAS669.png
Figure 49. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
C118_BAS669.png
Figure 51. Spurious-Free Dynamic Range vs
Input Frequency
C120_BAS669.png
Figure 53. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
C122_BAS669.gif
Figure 55. Performance vs Input Amplitude
(170 MHz)
C124_BAS669.png
Figure 57. Performance vs Input Common-Mode Voltage (170 MHz)
C126_BAS669.gif
Figure 59. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
C128_BAS669.gif
Figure 61. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
C130_BAS669.png
Figure 63. Performance vs Clock Amplitude
(150 MHz)
C132_BAS669.png
Figure 65. Performance vs Clock Duty Cycle
(150 MHz)

7.17 Typical Characteristics: ADC34J23

Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
C201_BAS669.png
fS = 80 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz, SFDR = 96.6 dBc
Figure 67. FFT for 10-MHz Input Signal (Dither On)
C203_BAS669.png
fS = 80 MSPS, SNR = 70 dBFS, fIN = 70 MHz, SFDR = 99.5 dBc
Figure 69. FFT for 70-MHz Input Signal (Dither On)
C205_BAS669.png
fS = 80 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz,
SFDR = 92.7 dBc
Figure 71. FFT for 170-MHz Input Signal (Dither On)
C207_BAS669.png
fS = 80 MSPS, SNR = 68.4 dBFS, fIN = 270 MHz,
SFDR = 76.4 dBc
Figure 73. FFT for 270-MHz Input Signal (Dither On)
C209_BAS669.png
fS = 80 MSPS, SNR = 65.5 dBFS, fIN = 450 MHz,
SFDR = 63.3 dBc
Figure 75. FFT for 450-MHz Input Signal (Dither On)
C211_BAS669.png
fS = 80 MSPS, IMD = 95 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 99 dBFS
Figure 77. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
C213_BAS669.png
fS = 80 MSPS, IMD = 88 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 94 dBFS
Figure 79. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
C215_BAS669.png
Figure 81. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
C217_BAS669.png
Figure 83. Signal-to-Noise Ratio vs Input Frequency
C219_BAS669.png
Figure 85. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
C221_BAS669.gif
Figure 87. Performance vs Input Amplitude
(30 MHz)
C223_BAS669.png
Figure 89. Performance vs Input Common-Mode Voltage
(30 MHz)
C225_BAS669.gif
Figure 91. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
C227_BAS669.gif
Figure 93. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
C229_BAS669.png
Figure 95. Performance vs Clock Amplitude
(40 MHz)
C231_BAS669.png
Figure 97. Performance vs Clock Duty Cycle
(40 MHz)
C233_BAS669.png
RMS noise = 1.4 LSBs
Figure 99. Idle Channel Histogram
C202_BAS669.png
fS = 80 MSPS, SNR = 70.6 dBFS, fIN = 10 MHz, SFDR = 90.3 dBc
Figure 68. FFT for 10-MHz Input Signal (Dither Off)
C204_BAS669.png
fS = 80 MSPS, SNR = 70.4 dBFS, fIN = 70 MHz, SFDR = 90.1 dBc
Figure 70. FFT for 70-MHz Input Signal (Dither Off)
C206_BAS669.png
fS = 80 MSPS, SNR = 69.6 dBFS, fIN = 10 MHz, SFDR = 92.9 dBc
Figure 72. FFT for 170-MHz Input Signal (Dither Off)
C208_BAS669.png
fS = 80 MSPS, SNR = 68.3 dBFS, fIN = 270 MHz,
SFDR = 76.9 dBc
Figure 74. FFT for 270-MHz Input Signal (Dither Off)
C210_BAS669.png
fS = 80 MSPS, SNR = 66.2 dBFS, fIN = 450 MHz,
SFDR = 62.9 dBc
Figure 76. FFT for 450-MHz Input Signal (Dither Off)
C212_BAS669.png
fS = 80 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 106 dBFS
Figure 78. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
C214_BAS669.png
fS = 80 MSPS, IMD = 100 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 102 dBFS
Figure 80. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
C216_BAS669.png
Figure 82. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
C218_BAS669.png
Figure 84. Spurious-Free Dynamic Range vs
Input Frequency
C220_BAS669.png
Figure 86. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
C222_BAS669.gif
Figure 88. Performance vs Input Amplitude
(170 MHz)
C224_BAS669.png
Figure 90. Performance vs Input Common-Mode Voltage (170 MHz)
C226_BAS669.gif
Figure 92. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
C228_BAS669.gif
Figure 94. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
C230_BAS669.png
Figure 96. Performance vs Clock Amplitude
(150 MHz)
C232_BAS669.png
Figure 98. Performance vs Clock Duty Cycle
(150 MHz)

7.18 Typical Characteristics: ADC34J22

Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
C301_BAS669.png
fS = 50 MSPS, SNR = 70.2 dBFS, fIN = 10 MHz, SFDR = 96.5 dBc
Figure 100. FFT for 10-MHz Input Signal (Dither On)
C303_BAS669.png
fS = 50 MSPS, SNR = 69.9 dBFS, fIN = 70 MHz, SFDR = 92.6 dBc
Figure 102. FFT for 70-MHz Input Signal (Dither On)
C305_BAS669.png
fS = 50 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz,
SFDR = 88.7 dBc
Figure 104. FFT for 170-MHz Input Signal (Dither On)
C307_BAS669.png
fS = 50 MSPS, SNR = 68.3 dBFS, fIN = 270 MHz,
SFDR = 76.9 dBc
Figure 106. FFT for 270-MHz Input Signal (Dither On)
C309_BAS669.png
fS = 50 MSPS, SNR = 66.1 dBFS, fIN = 450 MHz,
SFDR = 63.1 dBc
Figure 108. FFT for 450-MHz Input Signal (Dither On)
C311_BAS669.png
fS = 50 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 96 dBFS
Figure 110. FFT for Two-Tone Input Signal
(–7dBFS at 46 MHz and 50 MHz)
C313_BAS669.png
fS = 50 MSPS, IMD = 86 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 92 dBFS
Figure 112. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
C315_BAS669.png
Figure 114. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
C317_BAS669.png
Figure 116. Signal-to-Noise Ratio vs Input Frequency
C319_BAD669.png
Figure 118. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
C321_SBAS669.gif
Figure 120. Performance vs Input Amplitude
(30 MHz)
C323_BAS669.gif
Figure 122. Performance vs Input Common-Mode Voltage (30 MHz)
C325_BAS669.gif
Figure 124. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
C327_BAS669.gif
Figure 126. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
C329_BAS669.gif
Figure 128. Performance vs Clock Amplitude
(40 MHz)
C331_BAS669.png
Figure 130. Performance vs Clock Duty Cycle
(40 MHz)
C333_BAS669.png
RMS noise = 1.3 LSBs
Figure 132. Idle Channel Histogram
C302_BAS669.png
fS = 50 MSPS, SNR = 70.6 dBFS, fIN = 10 MHz, SFDR = 90.4 dBc
Figure 101. FFT for 10-MHz Input Signal (Dither Off)
C304_BAS669.png
fS = 50 MSPS, SNR = 70.3 dBFS, fIN = 70 MHz, SFDR = 88 dBc
Figure 103. FFT for 70-MHz Input Signal (Dither Off)
C306_BAS669.png
fS = 50 MSPS, SNR = 69.5 dBFS, fIN = 170 MHz,
SFDR = 88.5 dBc
Figure 105. FFT for 170-MHz Input Signal (Dither Off)
C308_BAS669.png
fS = 50 MSPS, SNR = 68.4 dBFS, fIN = 270 MHz,
SFDR = 76.5 dBc
Figure 107. FFT for 270-MHz Input Signal (Dither Off)
C310_BAS669.png
fS = 50 MSPS, SNR = 66.3 dBFS, fIN = 450 MHz,
SFDR = 63.2 dBc
Figure 109. FFT for 450-MHz Input Signal (Dither Off)
C312_BAS669.png
fS = 50 MSPS, IMD = 99 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 106 dBFs
Figure 111. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
C314_BAS669.png
fS = 50 MSPS, IMD = 99 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 102 dBFs
Figure 113. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
C316_BAS669.png
Figure 115. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
C318_BAD669.png
Figure 117. Spurious-Free Dynamic Range vs
Input Frequency
C320_BAD669.png
Figure 119. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
C322_BAS669.gif
Figure 121. Performance vs Input Amplitude
(170 MHz)
C324_BAS669.png
Figure 123. Performance vs Input Common-Mode Voltage (170 MHz)
C326_BAS669.gif
Figure 125. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
C328_BAS669.gif
Figure 127. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
C330_BAS669.png
Figure 129. Performance vs Clock Amplitude
(150 MHz)
C332_BAS669.png
Figure 131. Performance vs Clock Duty Cycle
(150 MHz)

7.19 Typical Characteristics: Common Plots

Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
D401_BAS669.gif
fS = 160 MSPS, fCM = 10 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fCM ) = –98 dBFS, Amplitude (fIN – fCM ) = –91 dBFS
Figure 133. Common-Mode Rejection Ratio FFT
D403_BAS669.gif
fS = 160 MSPS, fPSRR = 5 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fPSRR ) = –62 dBFS, Amplitude (fIN – fPSRR ) = –65.35 dBFS
Figure 135. Power-Supply Rejection Ratio FFT for
AVDD Supply
D405_BAS669.gif
Figure 137. Power vs Sampling Frequency
(20x Mode)
D402_BAS669.gif
Input frequency = 30 MHz, 50-mVPP signal superimposed on VCM
Figure 134. Common-Mode Rejection Ratio vs
Test Signal Frequency
D404_BAS669.gif
Input frequency = 30 MHz, 50-mVPP signal superimposed on VCM
Figure 136. Power-Supply Rejection Ratio vs
Test Signal Frequency
D406_BAS669.gif
Figure 138. Power vs Sampling Frequency
(40x Mode)

7.20 Typical Characteristics: Contour Plots

Typical values are at TA = 25°C, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
SFDR_0dB_BAS669.png
Figure 139. Spurious-Free Dynamic Range (SFDR) for 0-dB Gain
SFDR_6dB_BAS669.png
Figure 140. Spurious-Free Dynamic Range (SFDR) for 6-dB Gain
SNR_0dB_BAS669.png
Figure 141. Signal-to-Noise Ratio (SNR) for 0-dB Gain
SNR_6dB_BAS669.png
Figure 142. Signal-to-Noise Ratio (SNR) for 6-dB Gain