The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC34J2x Quad-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with JESD204B Interface datasheet (Rev. A) | PDF | HTML | 29 Jan 2015 |
| EVM User's guide | ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) | 24 Aug 2018 |
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The ADC34J24EVM Evaluation Module demonstrates the performance of a low power quad 125Msps 12 bit ADC. It includes the ADC34J24 device, JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages. The input for the ADC is by default connected to the (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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