SBASAI7 March 2023 ADC34RF52
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | RESET |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | R/W | 0 | Must write 0 |
0 | RESET | R/W | 0 | This bit resets all internal registers to the default values. Does not self clear to 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | ANALOG PAGE | CALIB PAGE | DDCCD PAGE | DDCAB PAGE | JESD PAGE | DIGITAL PAGE | 0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6 | ANALOG PAGE | R/W | 0 | This bit enables access to the ANALOG page 0: ANALOG page access disabled 1: ANALOG page access enabled |
5 | CALIB PAGE | R/W | 0 | This bit enables access to the CALIBRATION page 0: CALIBRATION page access disabled 1: CALIBRATION page access enabled |
4 | DDCCD PAGE | R/W | 0 | This bit enables access to the DDCCD page. Contents can be written to DDCAB and DDCCD page simultaneously if it is identical. 0: DDCCD page access disabled 1: DDCCD page access enabled. |
3 | DDCAB PAGE | R/W | 0 | This bit enables access to the DDCAB page. Contents can be written to DDCAB and DDCCD page simultaneously if it is identical. 0: DDCAB page access disabled 1: DDCAB page access enabled |
2 | JESD PAGE | R/W | 0 | This bit enables access to the JESD page 0: JESD page access disabled 1: JESD page access enabled |
1 | DIGITAL PAGE | R/W | 0 | This bit enables access to the DIGITAL page 0: DIGITAL page access disabled 1: DIGITAL page access enabled |
0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
20-BIT OUT | DDC BAND SEL | 0 | 0 | 0 | DDC REAL | BYP EN | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 20-BIT OUT | R/W | 0 | This bit enables the 20-bit output mode. It carries the output sample with 20-bit output resolution from the DDC and the sample is filled to 32-bit with 12 trailing 0s. 0: Normal operation 1: 20-bit output mode |
6-5 | DDC BAND SEL | R/W | 00 | Selects 1 or DDC per ADC when complex decimation is enabled 0: Single band 1: Dual band 2,3: not used |
4-2 | 0 | R | 0 | Must write 0 |
1 | DDC REAL | R/W | 0 | This bit enables real decimation filter (NCO = 0). BYP EN (D0) must be set to 0. 0: Complex decimation 1: Real decimation |
0 | BYP EN | R/W | 0 | This bit enables DDC bypass mode 0: Decimation filter enabled. Complex decimation by default unless D1 is set 1: Decimation filter bypass |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | DECIMATION | 0 | 0 | 0 | 0 | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6-4 | DECIMATION | R/W | 0 | Selects decimation. 0,1: not used 2: Decimation by 4 3: Decimation by 8 4: Decimation by 16 5: Decimation by 32 6: Decimation by 64 7: Decimation by 128 |
3-0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | AVG EN | AVG SEL (1) | 0 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | R/W | 0 | Must write 0 |
3 | AVG EN | R/W | 0 | This bit enables averaging 0: no average 1: ADC averaging enabled |
2-1 | AVG SEL (1) | R/W | 00 | Selects ADC averaging. Also AVG SEL (2) in CALIBRATION page needs to be set. 0: no average 1: 2 ADC average |
0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 1 | FORMAT | 0 | GBL PDN | 0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | 0 | R/W | 0 | Must write 0 |
4 | 1 | R/W | 0 | Must write 1 |
3 | FORMAT | R/W | 0 | This register bit determines the output data format in DDC bypass mode only. 0: Offset Binary 1: 2s Complement DDC mode only supports 2s complement output format. |
2 | 0 | R/W | 0 | Must write 0 |
1 | GBL PDN | R/W | 0 | This register bit enables global power down mode 0: normal operation 1: global power down mode enabled |
0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | MEM STROBE | MEM CH SEL | 0 | 0 | 0 | 0 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6 | MEM STROBE | R/W | 0 | This register enables fast power down mode 0: normal operation 1: fast power down mode enabled |
5-4 | MEM CH SEL | R/W | 0 | This register selects which ADC channel is used to fill up the capture sample buffer. Only 1 channel can be selected at a time and the samples are captured from the ADC core without averaging or decimation. 00: capture memory is filled from chA input 01: capture memory is filled from chB input 10: capture memory is filled from chC input 11: capture memory is filled from chD input |
0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCO2 CHB [1:0] | NCO1 CHB [1:0] | NCO2 CHA [1:0] | NCO1 CHA [1:0] | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | NCO2 CHB [1:0] | R/W | 00 | This register is used when selecting the NCO frequency for channel B, band 2 with the SPI interface in dual band DDC mode. |
5-4 | NCO1 CHB [1:0] | R/W | 00 | This register is used when selecting the NCO1 of channel B with the SPI interface. |
3-2 | NCO2 CHA [1:0] | R/W | 00 | This register is used when selecting the NCO frequency for channel A, band 2 with the SPI interface in dual band DDC mode. |
1-0 | NCO1 CHA [1:0] | R/W | 00 | This register is used when selecting the NCO1 of channel A with the SPI interface. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCO2 CHD [1:0] | NCO1 CHD [1:0] | NCO2 CHC [1:0] | NCO1 CHC [1:0] | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | NCO2 CHD [1:0] | R/W | 00 | This register is used when selecting the NCO frequency for channel D, band 2 with the SPI interface in dual band DDC mode. |
5-4 | NCO1 CHD [1:0] | R/W | 00 | This register is used when selecting the NCO1 of channel D with the SPI interface. |
3-2 | NCO2 CHC [1:0] | R/W | 00 | This register is used when selecting the NCO frequency for channel C, band 2 with the SPI interface in dual band DDC mode. |
1-0 | NCO1 CHC [1:0] | R/W | 00 | This register is used when selecting the NCO1 of channel C with the SPI interface. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | SYSREF X5 | SYSREF X4 | SYSREF X3 | SYSREF X2 | SYSREF X1 | SYSREF OR | 1 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 1 | R/W | 1 | Must write 1 |
6-2 | SYSREF X1..5 | R/W | 0 | These bits are the XOR flags from the SYSREF window monitoring circuitry. The sampling clock gets delayed internally by ~ 160 ps and used to capture the SYSREF signal. If a SYSREF signal transition happens within +/- 50 ps of the SYSREF capture the appropriate XOR flag gets raised. These bits are not sticky - they get overwritten with the next SYSREF rising edge. X1: Window from 110 ps to 135 ps after the rising sampling clock edge X2: Window from 135 ps to 160 ps after the rising sampling clock edge X3: Window from 160 ps to 176 ps after the rising sampling clock edge X4: Window from 176 ps to 192 ps after the rising sampling clock edge X5: Window from 192 ps to 208 ps after the rising sampling clock edge 0: No SYSREF transition detected 1: SYSREF transition detected within given window |
1 | SYSREF OR | R/W | 0 | This bit is the output of the five SYSREF XOR flags logically OR'ed together. 0: no SYSREF flag raised 1: one of the five SYSREF XOR flags is raised. |
0 | 1 | R/W | 1 | Must write 1 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | NCO SEL MODE | 0 | 0 | GPIO MODE | |||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6-5 | NCO SEL MODE | R/W | 00 | These bits select control of the NCO selection in complex decimation. 0: NCO selection using GPIO pins (GPIO MODE (D2-D0) needs to be set accordingly) 2: GPIO1/2 pins are used as a fast serial interface to only up NCO selection for each digital mixer others: not used |
4-3 | 0 | R/W | 0 | Must write 0 |
2-0 | GPIO MODE | R/W | 000 | This register sets the functionality of the two GPIO pins 0: GPIO pins are used as SYNC input (LVDS), GPIO1 = SYNCP, GPIO2 = SYNCM 1: GPIO1 is used as SYNC input (CMOS) 3: Both GPIO pins are used to select NCOs for the decimation filters 4: GPIO1 is used to disable the calibration 5: GPIO1 is used as start of SYSREF counter others: not used |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCO SEL SOURCE | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | NCO SEL SOURCE | R/W | 0 | This register works in conjuction with NCO SEL MODE (0x234). 0x00: NCO selection other than regular SPI (GPIO, Fast SPI etc) 0xFF: NCO selection using regular SPI with addresses 0x3B/41. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | GPIO2 INV | GPIO1 INV | GPIO SWAP | 0 | 0 | 0 | 0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6 | GPIO2 INV | R/W | 0 | This bit inverts polarity of the GPIO2 pin 0: Polarity as is 1: Polarity inverted |
5 | GPIO1 INV | R/W | 0 | This bit inverts polarity of the GPIO1 pin 0: Polarity as is 1: Polarity inverted |
4 | GPIO SWAP | R/W | 0 | This bit swaps GPIO1 and GPIO2 pins internally. 0: Normal operation 1: GPIO1 and GPIO2 are swapped |
3-0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVR OUTPUT CFG | 0 | 0 | 0 | 0 | |||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | OVR OUTPUT CFG | R/W | 0000 | This bit configures if the overrange indication (OVR) is output on JESD output stream or on GPIO pins 0000: OVR on JESD 1111: OVR on GPIO |
3-0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
K | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | K | R/W | 00000000 | This is JESD204B parameter K which sets number of frames in a multi-frame. Bit value is set as K minus 1. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | SYNC SPI EN | SYNC SPI | 0 | 0 | SYSREF MODE | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6 | SYNC SPI EN | R/W | 0 | This bit enables JESD SYNC control using SPI (ignoring SYNC using GPIO1/2 pins) using bit D5 (SYNC SPI). 0: SPI SYNC disabled 1: SPI SYNC (using register bit D5) enabled |
5 | SYNC SPI | R/W | 0 | This bit enables JESD SYNC. SYNC control via SPI must be enabled also (D6). 0: ADC outputs data (SYNC disabled) 1: SYNC enabled (ADC outputs K28.5 characters for JESD interface synchronization) |
4-3 | 0 | R/W | 0 | Must write 0 |
2-0 | SYSREF MODE | R/W | 000 | This register controls how the ADC processes incoming SYSREF pulses. 0: Ignore all SYSREF pulses 1: Use all SYSREF pulses 2: Don't use SYSREF pulses 3: Skip one SYSREF pulse then use only the next one 4: Skip one SYSREF pulse then use all pulses 5: Skip two SYSREF pulses and then use one 6: Skip two SYSREF pulses and then use all |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JESD MODE | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | JESD MODE | R/W | 00000000 | This register sets the LMFS configuration 1: LMFS = 8-2-2-4 2: LMFS = 8-4-8-10 (also bit DROP LSB in 0x27 needs to be set) 3: LMFS = 8-4-2-2 4: LMFS = 8-16-4-1 5: LMFS = 4-16-8-1 6: LMFS = 2-16-16-1 7: LMFS = 1-16-32-1 8: LMFS = 8-8-2-1 9: LMFS = 4-8-4-1 10: LMFS = 2-8-8-1 11: LMFS = 1-8-16-1 12: LMFS = 4-4-2-1 13: LMFS = 2-4-4-1 14: LMFS = 1-4-8-1 others: not used |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DDC CLK DIV | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DDC CLK DIV | R/W | 00000000 | This register sets the internal clock divider when using the decimation filter. See #GUID-2860BD61-8C68-48F5-AB10-AD477D98BAC0/TABLE_WCK_TJS_LPB |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JESD TX CLK DIV | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | JESD TX CLK DIV | R/W | 0000000 | This register sets the internal clock divider for the selected LMFS output mode. See #GUID-2860BD61-8C68-48F5-AB10-AD477D98BAC0/TABLE_WCK_TJS_LPB |
0x24 (DDC CLK DIV) | 0x25 (JESD TX CLK DIV) | |||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LMFS | BYP | /4 | /8 | /16 | /32 | /64 | /128 | BYP | /4 | /8 | /16 | /32 | /64 | /128 |
8-4-8-10 | 1 | 4 | ||||||||||||
8-4-2-2 | 1 | 0 | ||||||||||||
4-4-2-1 | 3 | 0 | ||||||||||||
8-8-2-1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
8-16-4-1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | ||||
4-8-4-1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||
4-16-8-1 | 3 | 3 | 3 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | ||||
2-8-8-1 | 3 | 3 | 3 | 3 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | ||
2-16-16-1 | 7 | 7 | 7 | 7 | 7 | 0 | 0 | 0 | 0 | 0 | ||||
1-8-16-1 | 7 | 7 | 7 | 7 | 7 | 0 | 0 | 0 | 0 | 0 | ||||
1-16-32-1 | 15 | 15 | 15 | 15 | 15 | 0 | 0 | 0 | 0 | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DROP LSB | 0 | 0 | 0 | CLK BAL EN | 0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | R/W | 0 | Must write 0 |
5 | DROP LSB | R/W | 0 | This register needs to be set when using the 12-bit output LMFS mode. 0: Drop LSB disabled 1: Drop LSB enabled when using LMFS = 8-4-8-10 |
4-2 | 0 | R/W | 0 | Must write 0 |
1 | CLK BAL EN | R/W | 0 | This register bit needs to be enabled in bypass mode LMFS = 8-4-2-2 only in order to improve some internal clock balancing. 0: CLK BAL disabled 1: CLK BAL EN. Set for LMFS = 8-4-2-2 |
0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JESD LANE EN | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | JESD LANE EN | R/W | 11111111 | This register turns on individual output lanes 0: Lane powered down 1: Serdes lane enabled D0: Lane DOUT0 D1: Lane DOUT1 ... D7: Lane DOUT7 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | SYNC INV |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | R/W | 0 | Must write 0 |
0 | SYNC INV | R/W | 0 | This register inverts the polarity from external SYNC pin 0: Polarity as is 1: Polarity inverted |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | JESD SEQ SEL | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | 0 | R/W | 0 | Must write 0 |
2-0 | JESD SEQ SEL | R/W | 000 | This register selects the JESD test pattern sequence 0: Test sequence disabled 1: Repeat D21.5 high frequency pattern for random jitter (RJ) 2: Repeat K28.5 mixed frequency pattern for deterministic jitter (DJ) 3: Repeat initial lane alignment (ILA) sequence 4: Modified random pattern 5: Scrambled jitter pattern 6: Repeat K28.7 low frequency pattern 7: Short test pattern |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMP INCR | 0 | RAMP EN | ALT PAT | 0 | |||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RAMP INCR | R/W | 0000 | This register value sets the increment step size for the ramp pattern on 16-bit output. The step size is RAMP INCR plus 1. |
3 | 0 | R/W | 0 | Must write 0 |
2 | RAMP EN | R/W | 0 | Enables RAMP output pattern in the TRANSPORT LAYER. |
1 | ALT PAT | R/W | 0 | Enables a toggle pattern switching between 0x0000 and 0xFFFF in the TRANSPORT LAYER |
0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | SERDES PRBS | SERDES PRBS EN | 0 | JESD PRBS | JESD PRBS EN | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6-5 | SERDES PRBS | R/W | 0 | This register selects the PRBS pattern in the LINK LAYER (no 8b/10b encoding). PRBS pattern must be enabled (D4). 0: PRBS 27-1 1: PRBS 215-1 2: PRBS 223-1 3: PRBS 231-1 |
4 | SERDES PRBS EN | R/W | 0 | This register enables PRBS test pattern in the LINK LAYER 0: Test pattern mode disabled 1: PRBS test pattern mode enabled |
3 | 0 | R/W | 0 | Must write 0 |
2-1 | JESD PRBS | R/W | 0 | This register selects the PRBS pattern in the TRANSPORT LAYER (test pattern will be 8b/10b encoded). PRBS pattern must be enabled (D0). 0: PRBS 27-1 1: PRBS 215-1 2: PRBS 223-1 3: PRBS 231-1 |
0 | JESD PRBS EN | R/W | 0 | This register enables PRBS test pattern in the TRANSPORT LAYER 0: Test pattern mode disabled 1: PRBS test pattern mode enabled |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
START VALUE JESD RAMP DOUT0/1/2/3/4/5/6/7 | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | START VALUE JESD RAMP DOUT0/1/2/3/4/5/6/7 | R/W | 00000000 | The JESD RAMP test pattern is designed to act as an individual RAMP pattern on each output lane. If the starting value on each lane is set to 0 (default) each output lane shows the same RAMP code at any given time. The RAMP pattern can be configured such that the RAMP pattern is constructed across JESD output lanes using the start value registers. DOUT1=1, DOUT2=2, DOUT3=3, DOUT4=0, DOUT5=1, DOUT6=2 and DOUT7=3 as well as the RAMP increment to 4 (RAMP INCR (0x2E) = 0x30) results in a RAMP pattern across lanes for each channel in bypass mode. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCR EN | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SCR EN | R/W | 0 | Enables scrambling of the JESD output data 0: Output scrambling disabled 1: Output scrambling enabled |
6-0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
F in ILA | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | F in ILA | R/W | 0 | These bits set F in the ILA sequence. Register value is actual F value -1 (0x01 = F(2)). |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
K in ILA | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | K in ILA | R/W | 0 | These bits set K in the ILA sequence. Register value is actual K value -1 (0x0F = K(15)) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JESD LANE POL INV | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | JESD LANE POL INV | R/W | 00000000 | This register inverts the polarity of the individual SERDES output lanes. Register bit D0 corresponds to SERDES lane DOUT0, D1 to DOUT1 etc 0: Output polarity as is 1: Output polarity inverted |
ADDR | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0x80 | 0 | LANE DOUT1 SEL | 0 | LANE DOUT0 SEL | ||||
0x81 | 0 | LANE DOUT3 SEL | 0 | LANE DOUT2 SEL | ||||
0x82 | 0 | LANE DOUT5 SEL | 0 | LANE DOUT4 SEL | ||||
0x83 | 0 | LANE DOUT7 SEL | 0 | LANE DOUT6 SEL | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7,3 | 0 | R/W | 0 | Must write 0 |
6-4 | LANE DOUT1/3/5/7 SEL | R/W | 000 | These register bits control the output mux. Any physical serdes output lane (DOUTx) can be connected to any JESD digital stream. By default lane DOUT0 is connected to JESD stream 0, lane DOUT1 to JESD stream 1 etc. 0: JESD stream 0 1: JESD stream 1 ... 7: JESD stream 7 |
2-0 | LANE DOUT0/2/4/6 SEL | R/W | 000 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | JESD PLL FACTOR | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | R/W | 0 | Must write 0 |
1-0 | JESD PLL FACTOR | R/W | 00 | This register bit must be set for 12-bit output LMFS = 8-4-8-10 only. 0: all other JESD LMFS modes 1: Set for LMFS = 8-4-8-10 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX EMPH DOUT1 [0] | TX EMPH DOUT0 [5:0] | 0 | |||||
0 | 0 | 0 | TX EMPH DOUT1 [5:1] | ||||
TX EMPH DOUT3 [0] | TX EMPH DOUT2 [5:0] | 0 | |||||
0 | 0 | 0 | TX EMPH DOUT3 [5:1] | ||||
TX EMPH DOUT5 [0] | TX EMPH DOUT4 [5:0] | 0 | |||||
0 | 0 | 0 | TX EMPH DOUT5 [5:1] | ||||
TX EMPH DOUT7 [0] | TX EMPH DOUT6 [5:0] | 0 | |||||
0 | 0 | 0 | TX EMPH DOUT7 [5:1] | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5,0 | 0 | R/W | 0 | Must write 0 |
6-1 | TX EMPH DOUT0/2/4/6 [5:0] | R/W | 000000 | These bits select the amount of de-emphasis for the JESD output transmitter. The de-emphasis value in dB is measured as the ratio between the peak value after the signal transition to the settled value of the voltage in one bit period. 0: 0 dB 1: –1 dB 3: –2 dB 7: –4.1 dB 15: –6.2 dB 31: –8.2 dB 63: –11.5 dB |
4-0,7 | TX EMPH DOUT1/3/5/7 [5:0] | R/W | 000000 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PD DOUT7 [0,1] | PD DOUT6 [0,1] | PD DOUT5 [0,1] | PD DOUT4 [0,1] | PD DOUT3 [0,1] | PD DOUT2 [0,1] | PD DOUT1 [0,1] | PD DOUT0 [0,1] |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PD DOUTx [0,1] | R/W | 0 | Register 0x9D and 0x9E allow power down of individual serdes output lanes. Register 0x9D (PD DOUTx [0]) covers the output driver, 0x9E (PD DOUTx [1]) covers the associated internal high-speed data clock. 0: Output lane enabled 1: Output lane powered down |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | JESD PLL1 | 0 | JESD PLL2 | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6-4 | JESD PLL1 | R/W | 000 | Internal JESD PLL input divider setting. See #GUID-2860BD61-8C68-48F5-AB10-AD477D98BAC0/TABLE_Q41_M4S_LPB how to configure it for the different decimation and LMFS settings. |
3 | 0 | R/W | 0 | Must write 0 |
2-0 | JESD PLL2 | R/W | 000 | Internal JESD PLL input divider setting. See #GUID-2860BD61-8C68-48F5-AB10-AD477D98BAC0/TABLE_Q41_M4S_LPB how to configure it for the different decimation and LMFS settings. |
ADDR | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0xA0 | 0 | JESD PLL INPUT1 | 0 | 0 | 0 | 0 | ||
0xA1 | 0 | JESD PLL INPUT2 | 0 | 0 | 0 | 0 | ||
0xA2 | 0 | 0 | 0 | 0 | JESD PLL INPUT3 | 0 | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | 0 | R/W | 0 | Must write 0 |
6-4 | JESD PLL INPUT1/2 | R/W | 000 | Internal JESD PLL input divider setting. See #GUID-2860BD61-8C68-48F5-AB10-AD477D98BAC0/TABLE_Q41_M4S_LPB how to configure it for the different decimation and LMFS settings. |
3-1 | JESD PLL INPUT3 | R/W | 000 | Internal JESD PLL input divider setting. See #GUID-2860BD61-8C68-48F5-AB10-AD477D98BAC0/TABLE_Q41_M4S_LPB how to configure it for the different decimation and LMFS settings. |
JESD PLL1/2, JESD PLL INPUT 2 | JESD PLL INPUT 1 | JESD PLL INPUT 3 | |||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LMFS | BYP | /4 | /8 | /16 | /32 | /64 | /128 | BYP | /4 | /8 | /16 | /32 | /64 | /128 | BYP | /4 | /8 | /16 | /32 | /64 | /128 |
8-4-8-10 | 0 | 0 | 1 | ||||||||||||||||||
8-4-2-2 | 0 | 0 | 1 | ||||||||||||||||||
4-4-2-1 | 0 | 0 | 3 | ||||||||||||||||||
8-8-2-1 | 0 | 1 | 2 | 3 | 4 | 5 | 0 | 1 | 2 | 3 | 4 | 5 | 0 | 1 | 0 | 0 | 0 | 0 | |||
8-16-4-1 | 0 | 1 | 2 | 3 | 4 | 0 | 0 | 1 | 2 | 3 | 4 | 0 | 0 | 0 | 0 | 0 | |||||
4-4-2-1 | 0 | 1 | 2 | 3 | 4 | 5 | 0 | 1 | 2 | 3 | 4 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | |||
4-8-4-1 | 0 | 0 | 1 | 2 | 3 | 4 | 0 | 0 | 1 | 2 | 3 | 4 | 1 | 0 | 0 | 0 | 0 | 0 | |||
4-16-8-1 | 0 | 0 | 1 | 2 | 3 | 0 | 0 | 0 | 1 | 2 | 3 | 1 | 0 | 0 | 0 | 0 | |||||
2-8-8-1 | 0 | 0 | 0 | 1 | 2 | 3 | 0 | 0 | 0 | 1 | 2 | 3 | 3 | 1 | 0 | 0 | 0 | 0 | |||
2-16-16-1 | 0 | 0 | 0 | 1 | 2 | 0 | 0 | 0 | 0 | 1 | 2 | 3 | 1 | 0 | 0 | 0 | |||||
1-8-16-1 | 0 | 0 | 0 | 1 | 2 | 0 | 0 | 0 | 1 | 2 | 3 | 1 | 0 | 0 | 0 | ||||||
1-16-32-1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 3 | 1 | 0 | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | JESD DDC BYP | 0 | 0 | 0 | 0 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | R/W | 0 | Must write 0 |
5-4 | JESD DDC BYP | R/W | 00 | This register needs to be set for the internal JESD frame assembly in DDC bypass output mode: 0: Any DDC mode 1: LMFS = 8-4-2-2 or 8-4-8-10 2: LMFS = 4-4-2-1 |
3-0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCOx FREQUENCYx [7:0],[15:8],[23:16],[31:24],[39:32],[47:40] | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
47:0 | NCOx CHAB/CD FREQUENCYx | R/W | 0 | The frequencies for NCOs are located in addresses 0x100 to 0x17D. Each frequency is 48-bit and the MSB starts on the highest address. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | LOAD NCO | 0 | 0 | 0 | 0 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | R/W | 0 | Must write 0 |
5-4 | LOAD NCO | R/W | 00 | This register loads all the NCO frequencies from the memory to the NCOs. To update the NCO this register has to be set to 3 and back to 0 as shown in #GUID-2860BD61-8C68-48F5-AB10-AD477D98BAC0/TABLE_DVD_LV5_4PB |
3-0 | 0 | R/W | 0 | Must write 0 |
ADDR | DATA | DESCRIPTION |
---|---|---|
0x105 | 0x4E | Frequency = 460 MHz with FS = 1.3 GSPS 99,598,837,913,001 = 0x5A95A95A95A9 where the MSB goes to address 0x105 and the LSB to 0x100. |
0x104 | 0x81 | |
0x103 | 0xB4 | |
0x102 | 0xE8 | |
0x101 | 0x1B | |
0x100 | 0x4E | |
0x181 | 0x00 | Load and update all NCO frequencies |
0x181 | 0x30 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | AVG SEL (2) | 1 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | 0 | R/W | 0 | Must write 0 |
2-1 | AVG SEL (2) | R/W | 00 | Selects ADC averaging. Also AVG SEL (1) in DIGITAL page needs to be set. 0: no average 01: 2 ADC average 10/11: not used |
0 | 1 | R/W | 1 | Must write 1 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAL SPI | CAL GPIO | 0 | 0 | 1 | 0 | 1 | 0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CAL SPI | R/W | 0 | This register triggers the calibration using SPI write. It needs to be toggled (0=>1=>0). |
6 | CAL GPIO | R/W | 0 | This register triggers the calibration using the GPIO1 pin. |
5-4 | 0 | R/W | 0 | Must write 0 |
3 | 1 | R/W | 1 | Must write 1 |
2 | 0 | R/W | 0 | Must write 0 |
1 | 1 | R/W | 1 | Must write 1 |
0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | CAL STATUS | |||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | R/W | 0 | Must write 0 |
3-0 | CAL STATUS | R/W | 0000 | This register can be used to check if calibration state machine has finished without any errors. A value of 0xE indicates successful calibration. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | TERM AB | 0 | 0 | 0 | 0 | TERM AB |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | R/W | 0 | Must write 0 |
5,0 | TERM AB | R/W | 00 | This register sets the internal termination resistor at the analog inputs for channel A and B. 0: 100 ohm differential termination 1: 50 ohm differential termination |
4-1 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | TERM CD | 0 | 0 | 0 | 0 | TERM CD |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | R/W | 0 | Must write 0 |
5,0 | TERM CD | R/W | 00 | This register sets the internal termination resistor at the analog inputs for channel C and D. 0: 100 ohm differential termination 1: 50 ohm differential termination |
4-1 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | DITH AMP1 | 0 | 0 | 0 | |||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6-3 | DITH AMP1 | R/W | 0000 | This register sets dither amplitude coarse gain. There are two recommended settings: 0000: Amplitude = 0 0011: Amplitude = 3 Here is a list of all the settings: 0000: Amplitude = 0 (smallest) 0001: Amplitude = 1 ... 1110: Amplitude = 14 1111: Amplitude = 15 (largest) |
2-0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DITHER DIS | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DITHER DIS | R/W | 0 | This register disables internal dither. 0: Dither enabled 1: Dither disabled |
6-5 | 0 | R/W | 0 | Must write 0 |
4 | 1 | R/W | 0 | Must write 1 |
3-0 | 0 | R/W | 0 | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DITHER DIVIDER | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DITHER DIVIDER | R/W | 0 | This register sets the dither divider frequency. SPI write is actual -1. For example a divider of 48 is 47 (0x2F). 0x00 (default) is a divide /50 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREF AC |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | R/W | 0 | Must write 0 |
0 | SYSREF AC | R/W | 0 | This register enables external AC coupling of the SYSREF input with internal biasing. 0: External DC coupling with internal 100 Ω termination 1: External AC coupling with internal biasing |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | DITH AMP2 | 0 | 0 | 0 | 0 | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | R/W | 0 | Must write 0 |
6-4 | DITH AMP2 | R/W | 0 | This register sets dither amplitude fine gain. There are two recommended settings: 000: Amplitude = 0 100: Amplitude = -4 Here is a list of all the settings: 000: Amplitude = 0 001: Amplitude = 1 010: Amplitude = 2 011: Amplitude = 3 (largest) 100: Amplitude = -4 (smallest) 101: Amplitude = -3 110: Amplitude = -2 111: Amplitude = -1 |
5-0 | 0 | R/W | 0 | Must write 0 |
ADDR | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0xE6 | TX SWING [0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0xE7 | 0 | 0 | 0 | 0 | 0 | 0 | TX SWING [2:1] | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | 0 | R/W | 0 | Must write 0 |
1,0,7 | TX SWING [2:0] | R/W | 000 | This register adjusts the output amplitude on all 8 serdes lanes. 0: 850 mVpp 1: 825 mVpp 2: 800 mVpp 3: 775 mVpp 4: 950 mVpp 5: 925 mVpp 6: 900 mVpp 7: 875 mVpp |