The ADC34RF52 is a single core 14-bit, 1.5-GSPS, quad channel analog to digital converter (ADC) that supports RF sampling with input frequencies up to 2.5 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -153 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -156 dBFS/Hz.
Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 μs.
The ADC34RF52 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps. There are only 2 serdes lanes per ADC channel.
The power efficient ADC architecture consumes 0.73 W/ch at 1.5-GSPS and provides power scaling with lower sampling rates.
PART NUMBER | PACKAGE(1) | MAX SAMPLING RATE |
---|---|---|
ADC34RF52 | QFN (64) | 1.5 GSPS |
DATE | REVISION | NOTES |
---|---|---|
March 2023 | * | Initial Release |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ANALOG INPUTS | |||
INAP | 14 | I | Differential analog input for channel A. 100 Ω differential internal termination. |
INAM | 15 | ||
INBP | 18 | I | Differential analog input for channel B. 100 Ω differential internal termination. |
INBM | 19 | ||
INCP | 35 | I | Differential analog input for channel C. 100 Ω differential internal termination. |
INCM | 34 | ||
INDP | 31 | I | Differential analog input for channel D. 100 Ω differential internal termination. |
INDM | 30 | ||
VCM | 26 | O | Common-mode voltage output for the analog inputs. |
CLOCK, SYNCHRONIZATION | |||
CLKP | 23 | I | Differential sampling clock input. 100 Ω differential internal termination. |
CLKM | 24 | ||
SYSREFP | 27 | I | Differential external synchronization input. |
SYSREFM | 28 | ||
CONTROL | |||
RESETb | 11 | I | Hardware reset. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD18. |
SEN | 57 | I | Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD18. |
SCLK | 55 | I | Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor. |
SDIO | 56 | I/O | Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor. |
GPIO1 | 39 | I/O | GPIO control pin. This pin is configured through SPI interface for power down or NCO control function. |
GPIO2 | 38 | I/O | GPIO control pin. This pin is configured through SPI interface for power down or NCO control function. |
SPISEL | 10 | I | Determines the functional of the SPI interface pins: either normal SPI for register programming or fast access to NCO selection only for fast frequency hopping. |
DIGITAL DATA INTERFACE | |||
DOUT0P | 4 | O | JESD204B high-speed serial data output interface pins for channels A to D. Output lanes can be reordered using the output MUX. |
DOUT0M | 5 | ||
DOUT1P | 1 | O | |
DOUT1M | 2 | ||
DOUT2P | 63 | O | |
DOUT2M | 64 | ||
DOUT3P | 60 | O | |
DOUT3M | 61 | ||
DOUT4P | 45 | O | |
DOUT4M | 44 | ||
DOUT5P | 48 | O | |
DOUT5M | 47 | ||
DOUT6P | 50 | O | |
DOUT6M | 49 | ||
DOUT7P | 53 | O | |
DOUT7M | 52 | ||
POWER SUPPLY | |||
AVDD18 | 17,20,29,32, 58 | I | Analog 1.8-V power supply |
AVDD12 | 13,16,21,33, 36 | I | Analog 1.2-V power supply |
CLKVDD | 25 | I | Clock 1.2-V power supply. Very sensitive to power supply noise. Directly impacts close in aperture phase noise. |
DVDD | 3,7,9,40,42, 46,54,59 | I | Digital 1.2-V power supply |
AGND | 12,37 | I | Analog ground, shorted to thermal pad. |
CLKGND | 22 | I | Clock ground. |
DGND | 6,8,41,43,51,62 | I | Digital ground. |