The following screen shot shows the top layer of the ADC34RF52 EVM.
The input signal traces are routed as differential signals on the top layer
avoiding vias. Care is taken to maintain symmetry between positive and negative
input with matched trace length to minimize phase imbalance. #X8395 shows the
layout example for 1x and 2x averaging configuration
JESD204B output interface lanes are routed differential and length matched
Bypass caps are close to the power pins on the top layer avoiding vias.