SBASAI7 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5.5 NCO Frequency programming using the SPI interface

There are 2 separate NCOs per channel - one for each band (that is, NCO1 = band 1) and 4 different frequencies can be programmed per NCO as shown in #FIG_WLQ_MD4_MPB. The NCO frequencies are located in the DDCAB/CD pages (0x05 0x08 for channel A/B and 0x05 0x10 for channel C/D) in registers 0x100 to 0x17D. Depending on # of bands used, the frequencies for each NCO are selected in registers 0x3B and 0x41 (DIGITAL page) as shown in Table 7-21. If the NCO frequencies are the same for channel A/B and channel C/D, the frequencies can be written to both DDCAB and DDCCD pages simultaneously by selecting both pages (0x05 0x18).

Figure 7-37 Multi-Band NCO

Single band DDC uses the frequencies of both NCO1 and NCO2 for a combined 8 different frequencies for NCO1 using 3 bit control (NCO2 CHx [1] and NCO1 CHx [1:0]). The NCO2 selection bit (D3) decides if frequencies from NCO1 or NCO2 are being used. In dual and quad band DDC operating mode, there are 4 frequencies per NCO available and selected using 2 register bits (NCOx CHx [1:0]).

.
Table 7-21 NCO Frequency Selection SPI Interface Registers
# OF BANDS ADDR D7 D6 D5 D4 D3 D2 D1 D0
SINGLE 0x3B NCO2 CHB [1] 0 NCO1 CHB [1:0] NCO2 CHA [1] 0 NCO1 CHA [1:0]
0x41 NCO2 CHD [1] 0 NCO1 CHD [1:0] NCO2 CHC [1] 0 NCO1 CHC [1:0]
DUAL 0x3B NCO2 CHB [1:0] NCO1 CHB [1:0] NCO2 CHA [1:0] NCO1 CHA [1:0]
0x41 NCO2 CHD [1:0] NCO1 CHD [1:0] NCO2 CHC [1:0] NCO1 CHC [1:0]

To select a different frequency for the NCO, two registers (0x3B and 0x41) in the DIGITAL page must be updated. Assuming a SPI clock frequency of 10 MHz (100 ns period), programming two registers (2x (16 bit address and 8 bit data) = 48 bit) means that the NCO frequency would be updated in ~ 5 us.

When updating the currently being used NCO frequency to a new frequency, the following command has to be written to load the new frequency into the NCO - 0x181 0x00/0x30 in each of the DDCAB/CD pages.

Table 7-22 Example Register Writes
ADDR DATA DESCRIPTION
0x05 0x02 Select DIGITAL page
0x3B 0x01 Select frequency 2 for NCO1 of channel A.
0x235 0xFF Select NCO using SPI
0x05 0x08 Select DDCAB page
0x10D...0x108 0x.. Write new frequency in frequency 2 of NCO1 of channel A
0x181 0x00 Update NCO with current frequencies from the register map.
0x181 0x30

The NCO phase accumulators can be reset using the external SYSREF signal. A SYSREF mask can be setup such the SYSREF signal only goes to the NCO and the remaining device remains unaffected. The following register writes configure the SYSREF mask to only affect the NCO. After completion, the SYSREF mask should be set back to default.

Table 7-23 Example Register Writes to configure the SYSREF MASK
ADDR DATA DESCRIPTION
0x05 0x18 Select DDCAB/CD page
0x181 0x40 Reset NCO phases with SYSREF toggle
0x05 0x02 Select DIGITAL page
0x357 0xA2 SYSREF mask settings (0x00 is mask default)
0x358 0x02 SYSREF mask settings (0x00 is mask default)