The ADC364x family of devices are low-noise, ultra-low power, 14-bit, 10-MSPS to 65-MSPS dual-channel, high-speed analog-to-digital converters (ADCs). Designed for low power consumption, these devices deliver a noise spectral density of –155 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC364x offers very good dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 72 mW/ch at 65 MSPS, and power consumption scales well with lower sampling rates.
The ADC364x use a DDR or serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to +105⁰C.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
ADC364x | VQFN (40) | 5.00 × 5.00 mm |
PART NUMBER | RESOLUTION | SAMPLING RATE |
---|---|---|
ADC3643 | 14 BIT | 65 MSPS |
ADC3642 | 14 BIT | 25 MSPS |
ADC3641 | 14 BIT | 10 MSPS |
Changes from Revision * (October 2020) to Revision A (May 2022)
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
INPUT/REFERENCE | |||
AINM | 13 | I | Negative analog input, channel A |
AINP | 12 | I | Positive analog input, channel A |
BINP | 39 | I | Positive analog input, channel B |
BINM | 38 | I | Negative analog input, channel B |
REFBUF | 4 | I | 1.2 V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions. |
REFGND | 3 | I | Reference ground input, 0 V |
VCM | 8 | O | Common-mode voltage output for the analog inputs, 0.95 V |
VREF | 2 | I | External voltage reference input |
CLOCK | |||
CLKM | 7 | I | Negative differential sampling clock input for the ADC |
CLKP | 6 | I | Positive differential sampling clock input for the ADC |
CONFIGURATION | |||
PDN/SYNC | 1 | I | Power down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor. |
RESET | 9 | I | Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor. |
SCLK | 35 | I | Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor. |
SDIO | 10 | I | Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor. |
SEN | 16 | I | Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD. |
DIGITAL INTERFACE | |||
DA0 | 17 | O | CMOS digital data output. |
DA1 | 18 | I/O | CMOS digital data output. Used as FCLK frame clock output for serialized CMOS output modes. Configured using SPI. |
DA2 | 19 | O | CMOS digital data output. |
DA3 | 20 | O | CMOS digital data output. |
DA4 | 22 | O | CMOS digital data output. |
DA5 | 23 | O | CMOS digital data output. |
DA6 | 24 | O | CMOS digital data output. |
DB0 | 34 | O | CMOS digital data output. |
DB1 | 33 | I/O | CMOS digital data output. Used as DCLKIN bit clock input for serialized CMOS output modes. Configured using SPI. |
DB2 | 32 | O | CMOS digital data output. |
DB3 | 31 | O | CMOS digital data output. |
DB4 | 29 | O | CMOS digital data output. |
DB5 | 28 | O | CMOS digital data output. |
DB6 | 27 | O | CMOS digital data output. |
DCLK | 25 | O | CMOS output for data bit clock. |
POWER SUPPLY | |||
AVDD | 5,15,36 | I | Analog 1.8-V power supply |
GND | 11,14,37,40, PowerPAD | I | Ground, 0 V |
IOGND | 26 | I | Ground, 0 V for digital interface |
IOVDD | 21,30 | I | 1.8-V power supply for digital interface |