The ADC3668 and ADC3669 (ADC366x) are a 16-bit, 250MSPS and 500MSPS, dual channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of −160dBFS/Hz (500MSPS).
The ADC366x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.
The ADC366x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 16-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.
The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).
PART NUMBER | PACKAGE(1) | MAXIMUM SAMPLING RATE |
---|---|---|
ADC3669 | 64 QFN | 500MSPS |
ADC3668 | 64 QFN | 250MSPS |
Part Number | Maximum Sampling Rate | Resolution | No. of Channels |
---|---|---|---|
ADC3669 | 500MSPS | 16 bit | 2 |
ADC3668 | 250MSPS | 16 bit | 2 |
ADC3569 | 500MSPS | 16 bit | 1 |
ADC3568 | 250MSPS | 16 bit | 1 |
ADC3649 | 500MSPS | 14 bit | 2 |
ADC3648 | 250MSPS | 14 bit | 2 |
ADC3549 | 500MSPS | 14 bit | 1 |
ADC3548 | 250MSPS | 14 bit | 1 |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 16, 33 | I | Analog ground, 0V |
AINM | 19 | I | Channel A differential signal input, negative connection. The differential input has programmable internal termination (100Ω or 200Ω) and is self biased. |
AINP | 18 | I | Channel A differential signal input, positive connection. |
AVDD12 | 15, 22, 34 | I | Analog 1.2V supply |
AVDD18 | 17, 20, 29, 32 | I | Analog 1.8V supply |
BINM | 30 | I | Channel B differential signal input, negative connection. The differential input has programmable internal termination (100Ω or 200Ω) and is self biased. |
BINP | 31 | I | Channel B differential signal input, positive connection. |
CLKGND | 23, 26 | I | Clock ground, 0V |
CLKP | 24 | I | Device sampling clock differential input. AC coupling and terminating the clock signal externally for best AC performance is recommended. The differential input is self biased to the input common-mode voltage (0.75V). |
CLKM | 25 | I | |
DCLKP | 55 | O | Differential LVDS data bit clock output. |
DCLKM | 56 | O | |
DGND | 1, 48, 57 | I | Digital ground, 0V |
DOUT0/FCLKM | 37 | O | Differential LVDS data bit output lane 0. In decimation mode, this pin turns to the differential SLVDS frame clock output, replacing the LSB. |
DOUT0/FCLKP | 38 | O | |
DOUT1M | 39 | O | Differential LVDS data bit output lane 1. Can be left floating and powered down via SPI if not used. |
DOUT1P | 40 | O | |
DOUT2M | 41 | O | Differential LVDS data bit output lane 2. Can be left floating and powered down via SPI if not used. |
DOUT2P | 42 | O | |
DOUT3M | 43 | O | Differential LVDS data bit output lane 3. Can be left floating and powered down via SPI if not used. |
DOUT3P | 44 | O | |
DOUT4M | 45 | O | Differential LVDS data bit output lane 4. Can be left floating and powered down via SPI if not used. |
DOUT4P | 46 | O | |
DOUT5P | 49 | O | Differential LVDS data bit output lane 5. Can be left floating and powered down via SPI if not used. |
DOUT5M | 50 | O | |
DOUT6P | 51 | O | Differential LVDS data bit output lane 6. Can be left floating and powered down via SPI if not used. |
DOUT6M | 52 | O | |
DOUT7P | 53 | O | Differential LVDS data bit output lane 7. Can be left floating and powered down via SPI if not used. |
DOUT7M | 54 | O | |
DOUT8M | 59 | O | Differential LVDS data bit output lane 8. Can be left floating and powered down via SPI if not used. |
DOUT8P | 60 | O | |
DOUT9M | 61 | O | Differential LVDS data bit output lane 9. Can be left floating and powered down via SPI if not used. |
DOUT9P | 62 | O | |
DOUT10M | 63 | O | Differential LVDS data bit output lane 10. Can be left floating and powered down via SPI if not used. |
DOUT10P | 64 | O | |
DOUT11P | 3 | O | Differential LVDS data bit output lane 11. Can be left floating and powered down via SPI if not used. |
DOUT11M | 4 | O | |
DOUT12P | 5 | O | Differential LVDS data bit output lane 12. Can be left floating and powered down via SPI if not used. |
DOUT12M | 6 | O | |
DOUT13P | 7 | O | Differential LVDS data bit output lane 13. Can be left floating and powered down via SPI if not used. |
DOUT13M | 8 | O | |
DOUT14P | 9 | O | Differential LVDS data bit output lane 14. Can be left floating and powered down via SPI if not used. |
DOUT14M | 10 | O | |
DOUT15P | 11 | O | Differential LVDS data bit output lane 15. Can be left floating and powered down via SPI if not used. |
DOUT15M | 12 | O | |
DVDD12 | 2, 47 | I | Digital 1.2V supply |
DVDD18 | 58 | I | Digital 1.8V supply |
GPIO0 | 27 | I/O | Synchronization or control input or status output or external voltage reference (1.2V). Can be left floating if not used. |
GPIO1 | 28 | I/O | Synchronization or control input or status output or external voltage reference (1.2V). Can be left floating if not used. |
RESET | 35 | I | Hardware reset. Active high. This pin has an internal 21kΩ pull-down resistor to DGND. |
SCLK | 13 | I | Serial interface clock for the serial interface programming. This pin has an internal 21kΩ pull-up resistor to DGND. |
SDIO | 36 | I/O | Serial interface data input/output. This pin has an internal 21kΩ pull-up resistor to DGND. |
SEN | 14 | I | Serial interface chip select. This pin has an internal 21kΩ pull-up resistor to DVDD18. |
VCM | 21 | O | Common mode voltage output (1.4V) |