ADC3669
16-bit two-channel 500MSPS ADC with LVDS interface and up to 32768x decimation
ADC3669
- 16-bit, dual channel 250 and 500MSPS ADC
- Noise spectral density: -160.4dBFS/Hz
- Thermal Noise: 76.4dBFS
- Single core (non-interleaved) ADC architecture
- Aperture jitter: 75fs
- Buffered analog inputs
- Programmable 100Ω and 200Ω termination
- Input fullscale: 2VPP
- Full power input bandwidth (-3dB): 1.4GHz
- Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 75.6dBFS
- SFDR HD2,3: 80dBc
- SFDR worst spur: 94dBFS
- INL: ±2 LSB (typical)
- DNL: ±0.5 LSB (typical)
- Digital down-converters (DDCs)
- Up to four independent DDCs
- Complex and real decimation
- Decimation: /2, /4 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
- DDR/Serial LVDS interface
- 16-bit Parallel DDR LVDS for DDC bypass
- Serial LVDS for decimation
- 32-bit output option for high decimation
- Power consumption: 300mW/channel (500MSPS)
The ADC3668 and ADC3669 (ADC366x) are a 16-bit, 250MSPS and 500MSPS, dual channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of −160dBFS/Hz (500MSPS).
The ADC366x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.
The ADC366x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 16-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.
The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | ADC3668, ADC3669 Dual-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet | PDF | HTML | 24 Sep 2024 |
Application note | The Fine Art of Passive Matching a High-Speed A/D Converter Analog Input Frontend | PDF | HTML | 13 Dec 2024 | |
Analog Design Journal | 被動匹配高速 ADC 類比輸入前端的藝術 | PDF | HTML | 09 Oct 2024 | |
Analog Design Journal | 고속 ADC 아날로그 입력 프론트 엔드를 패시브 매칭하는 기술 | PDF | HTML | 09 Oct 2024 | |
Analog Design Journal | The art of passive matching a high-speed ADC analog-input front end | PDF | HTML | 23 Sep 2024 | |
Certificate | ADC3669EVM EU Declaration of Conformity (DoC) (Rev. A) | 11 Sep 2024 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
ADC3669EVM — ADC3669 evaluation module
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
VQFNP (RTD) | 64 | Ultra Librarian |
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