ADS8912B
18-Bit, 500-kSPS, 1-Ch SAR ADC with Internal VREF Buffer, Internal LDO and Enhanced SPI Interface
ADS8912B
- Resolution: 18-Bits
- High Sample Rate With No Latency Output:
- ADS8910B: 1-MSPS
- ADS8912B: 500-kSPS
- ADS8914B: 250-kSPS
- Integrated LDO Enables Single-Supply Operation
- Low-Power Reference Buffer With No Droop
- Excellent AC and DC Performance:
- SNR: 102.5-dB, THD: –125-dB
- INL: ±0.5-LSB
- DNL: ±0.2-LSB, 18-Bit No-Missing-Codes
- Wide Input Range:
- Unipolar Differential Input Range: ±VREF
- VREF Input Range: 2.5-V to 5-V
- Single-Supply, Low-Power Operation
(Includes Internal Reference Buffer and LDO)- ADS8910B : 21-mW at 1-MSPS
- ADS8912B : 16-mW at 500-kSPS
- ADS8914B : 14-mW at 250-kSPS
- Enhanced-SPI Digital Interface
- Interface SCLK: 20-MHz at 1-MSPS
- Configurable Data Parity Output
- Extended Temperature Range: –40°C to +125°C
- Small Footprint: 4-mm × 4-mm VQFN
The ADS8910B, ADS8912B, and ADS8914B (ADS891xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 18-bit successive approximation register (SAR) analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS892xB (16-bit) resolution variants.
The ADS891xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS891xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
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Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | ADS891xB 18-Bit, High-Speed SAR ADCs With Integrated Reference Buffer and Enhanced Performance Features datasheet (Rev. B) | PDF | HTML | 26 Jan 2018 |
Circuit design | High-input impedance, true differential, AFE attenuator circuit for SAR ADCs (Rev. B) | PDF | HTML | 25 Sep 2024 | |
Circuit design | Single-ended to differential using a two op-amp circuit (Rev. A) | PDF | HTML | 20 Sep 2024 | |
Application note | Attenuator Amplifier Design to Maximize the Input Voltage of Differential ADCs | 14 Jun 2018 | ||
Application brief | Improving Input Settling for Precision Data Converters | 12 Dec 2017 | ||
Application brief | Optimizing Data Transfer on High-Resolution, High-Throughput Data Converters | 12 Dec 2017 | ||
Application brief | Simplify Isolation Designs Using an Enhanced-SPI ADC Interface | 11 Dec 2017 | ||
White paper | Enabling Faster, Smarter, and More Robust Solutions for SAR ADSx With multiSPI | 08 Nov 2016 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
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Supported products & hardware
Products
Precision op amps (Vos<1mV)
General-purpose op amps
Audio op amps
Transimpedance amplifiers
High-speed op amps (GBW ≥ 50 MHz)
Power op amps
Video amplifiers
Line drivers
Transconductance amplifiers & laser drivers
Fully differential amplifiers
Precision ADCs
Biosensing AFEs
High-speed ADCs (≥10 MSPS)
Receivers
Touchscreen controllers
Difference amplifiers
Instrumentation amplifiers
Audio line receivers
Analog current-sense amplifiers
Digital power monitors
Analog current-sense amplifiers with integrated shunt resistor
Digital power monitors with integrated shunt resistor
Die & wafer services
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
TINA-TI — SPICE-based analog simulation program
TIPD211 — 20-bit, 1-MSPS, 4-Ch Small Form Factor Design for Test and Measurement Applications Reference Design
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
VQFN (RGE) | 24 | Ultra Librarian |
Ordering & quality
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