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ADS54J69

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Dual-Channel, 16-Bit, 500-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS54J69

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 74.2 ENOB (bit) 12 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 74.2 ENOB (bit) 12 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 16-Bit Resolution, Dual-Channel, 500-MSPS ADC
  • Idle Channel Noise Floor: –159 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 73 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 93 dBc
    • SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone)
  • Spectral Performance (fIN = 310 MHz at –1 dBFS):
    • SNR: 71.7 dBFS
    • NSD: –155.7 dBFS/Hz
    • SFDR: 81 dBc
    • SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Decimate-by-2 Filter
  • JESD204B Interface with Subclass 1 Support:
    • 1 Lane per ADC at 10.0 Gbps
    • 2 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/ch at 500 MSPS
  • 72-Pin VQFNP Package (10 mm × 10 mm)
  • 16-Bit Resolution, Dual-Channel, 500-MSPS ADC
  • Idle Channel Noise Floor: –159 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 73 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 93 dBc
    • SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone)
  • Spectral Performance (fIN = 310 MHz at –1 dBFS):
    • SNR: 71.7 dBFS
    • NSD: –155.7 dBFS/Hz
    • SFDR: 81 dBc
    • SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Decimate-by-2 Filter
  • JESD204B Interface with Subclass 1 Support:
    • 1 Lane per ADC at 10.0 Gbps
    • 2 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/ch at 500 MSPS
  • 72-Pin VQFNP Package (10 mm × 10 mm)

The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.

The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.
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* Data sheet ADS54J69 Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter datasheet (Rev. C) PDF | HTML 20 Jan 2017
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024

Design & development

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Evaluation board

ADS54J69EVM — ADS54J69 Dual-Channel, 16-Bit, 500-MSPS Analog-to-Digital Converter Evaluation Module

The ADS54J69EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J69 and LMK04828 clock jitter cleaner. The ADS54J69 is a low power, 16-bit, 500-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

User guide: PDF
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Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
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Simulation model

ADS54J69 IBIS Model

SBAM257.ZIP (43 KB) - IBIS Model
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Simulation model

ADS54J69_IBIS_AMI_MODEL

SBAM258.ZIP (1953 KB) - IBIS-AMI Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFNP (RMP) 72 Ultra Librarian
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