ADS61B29
- Integrated High Impedance Analog Input Buffer
- Maximum Sample Rate: 250 MSPS
- 14-Bit Resolution — ADS61B49
- 12-Bit Resolution — ADS61B29
- 790 mW Total Power Dissipation at 250 MSPS
- Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
- Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off and 1-Vpp Full-Scale Operation
- DC Offset Correction
- Supports Input Clock Amplitude Down to 400 mVPP Differential
- 48-QFN Package (7mm × 7mm)
- Pin Compatible with ADS6149 Family
- APPLICATIONS
- Multicarrier, Wide Bandwidth Communications
- Wireless Multi-Carrier Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization Feedback ADC
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems
The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range.
The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (-40°C to 85°C).
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | 14-/12-Bit, 250-MSPS ADCs with Integrated Analog Input Buffer datasheet (Rev. B) | 13 May 2009 | |
Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 22 May 2015 | ||
Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 19 Jul 2013 | ||
Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 10 Sep 2010 | ||
EVM User's guide | ADS61x9/55xxEVM User's Guide (Rev B of the EVM board) (Rev. A) | 11 Jun 2009 | ||
Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 28 Apr 2009 | ||
Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 04 Sep 2008 | ||
Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08 Jun 2008 | ||
Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 02 Jun 2008 | ||
Application note | QFN Layout Guidelines | 28 Jul 2006 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
Supported products & hardware
Products
Precision op amps (Vos<1mV)
General-purpose op amps
Audio op amps
Transimpedance amplifiers
High-speed op amps (GBW ≥ 50 MHz)
Power op amps
Video amplifiers
Line drivers
Transconductance amplifiers & laser drivers
Fully differential amplifiers
Precision ADCs
Biosensing AFEs
High-speed ADCs (≥10 MSPS)
Touchscreen controllers
Difference amplifiers
Instrumentation amplifiers
Audio line receivers
Analog current-sense amplifiers
Digital power monitors
Analog current-sense amplifiers with integrated shunt resistor
Digital power monitors with integrated shunt resistor
Die & wafer services
RF receivers
RF transmitters
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
Supported products & hardware
Products
High-speed ADCs (≥10 MSPS)
Precision ADCs
SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
Supported products & hardware
Products
High-speed ADCs (≥10 MSPS)
RF receivers
Hardware development
Evaluation board
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
VQFN (RGZ) | 48 | Ultra Librarian |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
- Fab location
- Assembly location
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.