The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom
receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps
with one lane per channel. The buffered analog input provides uniform input impedance across a wide
frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent
spurious-free dynamic range (SFDR) over a large input frequency range with very low power
consumption. The digital signal processing block includes complex mixers followed by low-pass
filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63
also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD
observation receiver.
The JESD204B interface reduces the number of interface lines, thus allowing high system
integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital
converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data
from each channel.
The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom
receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps
with one lane per channel. The buffered analog input provides uniform input impedance across a wide
frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent
spurious-free dynamic range (SFDR) over a large input frequency range with very low power
consumption. The digital signal processing block includes complex mixers followed by low-pass
filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63
also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD
observation receiver.
The JESD204B interface reduces the number of interface lines, thus allowing high system
integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital
converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data
from each channel.