DAC38J84
Quad-Channel, 16-Bit, 2.5-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)
DAC38J84
- Resolution: 16-Bit
- Maximum Sample Rate:
- DAC37J84: 1.6 GSPS
- DAC38J84: 2.5 GSPS
- Maximum Input Data Rate: 1.23GSPS
- JESD204B Interface
- 8 JESD204B Serial Input Lanes
- 12.5 Gbps Maximum Bit Rate per Lane
- Subclass 1 Multi-DAC Synchronization
- On-Chip Very Low Jitter PLL
- Selectable 1x -16x Interpolation
- Independent Complex Mixers with 48-bit NCO/
or ±n×Fs/8 - Wideband Digital Quadrature Modulator Correction
- Sinx/x Correction Filters
- Fractional Sample Group Delay Correction
- Multi-Band Mode: Digital Summation of Independent
Complex Signals - 3/4-Wire Serial Control Bus (SPI):1.5V – 1.8V
- Integrated Temperature Sensor
- JTAG Boundary Scan
- Terminal-Compatible with Dual-Channel DAC37J82/
DAC38J82 Family - Power Dissipation: 1.8W at 2.5GSPS
- Package: 10x10mm, 144-Ball Flip-Chip BGA
The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
DAC38J84EVM — DAC38J84 Quad-Channel, 16-Bit, 2.5-GSPS, 1x-16x Interpolating DAC Evaluation Module
The DAC3XJ8XEVM is an evaluation module (EVM) designed to evaluate the DAC3XJ8X family of high-speed, JESD204B interface DACs (DAC37J82, DAC37J84, DAC38J82, DAC38J84). The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use (...)
TI204C-IP — Request for JESD204 rapid design IP
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Supported products & hardware
Products
High-speed DACs (>10 MSPS)
High-speed ADCs (≥10 MSPS)
RF transceivers
RF transmitters
DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.20
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
Supported products & hardware
Products
High-speed DACs (>10 MSPS)
High-speed ADCs (≥10 MSPS)
Ultrasound AFEs
RF transceivers
RF receivers
RF transmitters
Hardware development
Evaluation board
Software
Support software
SLAC644 — DAC3XJ8XEVM Software
Supported products & hardware
Products
High-speed DACs (>10 MSPS)
Hardware development
Evaluation board
SLAC661 — TSW3xJ8xEVM Software
Supported products & hardware
Products
High-speed DACs (>10 MSPS)
IQ modulators
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
TIDA-00684 — High-Bandwidth Arbitrary Waveform Generator Reference Design: DC or AC coupled, High-Voltage output
TIDEP0081 — Wideband Receiver Design Using 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design
TIDEP0060 — Optimized Radar System Reference Design Using a DSP+ARM SoC
TIDEP0034 — 66AK2L06 DSP+ARM Processor with JESD204B Attach to Wideband ADCs and DACs
TIDA-00996 — Synchronized Multi-Transmitter Reference Design: Method of Time-Aligning Multiple DACs
TIDA-00409 — 1-GHz Bandwidth Dual Channel Transmitter up to 4-GHz Reference Design
TIDA-00335 — High Bandwidth, High Frequency Transmitter Reference Design
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
FCCSP (AAV) | 144 | Ultra Librarian |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
- Fab location
- Assembly location
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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