Firmware
ADC12DJ5200RF
RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS
Data sheet
ADC12DJ5200RF
- ADC core:
- 12-bit resolution
- Up to 10.4GSPS in single-channel mode
- Up to 5.2GSPS in dual-channel mode
- Performance specifications:
- Noise floor (–20dBFS, VFS = 1VPP-DIFF):
- Dual-channel mode: –151.8dBFS/Hz
- Single-channel mode: –154.4dBFS/Hz
- ENOB (dual channel, FIN = 2.4GHz): 8.6 Bits
- Noise floor (–20dBFS, VFS = 1VPP-DIFF):
- Buffered analog inputs with VCMI of 0V:
- Analog input bandwidth (–3dB): 8GHz
- Usable input frequency range: > 10GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (tAD) adjustment:
- Precise sampling control: 19fs Step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204C serial data interface:
- Maximum lane rate: 17.16Gbps
- Support for 64b/66b and 8b/10b encoding
- 8b/10b modes are JESD204B compatible
- Optional digital down-converters (DDC):
- 4x, 8x, 16x and 32x complex decimation
- Four independent 32-Bit NCOs per DDC
- Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
- Programmable FIR filter for equalization
- Power consumption: 4W
- Power supplies: 1.1V, 1.9V
The ADC12DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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Technical documentation
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View all 19 Design & development
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Evaluation board
ADC12DJ5200RFEVM — ADC12DJ5200RF RF-sampling 12-bit dual 5.2-GSPS or single 10.4-GSPS ADC evaluation module
The ADC12DJ5200RF evaluation module (EVM) allows for the evaluation of device ADC12DJ5200RF. The ADC12DJ5200RF is a low-power, 12-bit, dual 5.2-GSPS/single 10.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO (...)
Evaluation board
TRF1208-ADC12DJ5200RFEVM — TRF1208 evaluation module for high-speed RF-sampling fully-differential amplifier with ADC12DJ5200RF
The TRF1208-ADC12DJ5200RFEVM is used to evaluate the ADC12DJ5200RF and ADC12DJ4000RF analog-to-digital converters (ADCs). The ADC12DJ5200RF is a dual-channel 12-bit ADC capable of operating at sampling rates up to 5.2 GSPS in dual-channel mode or 10.4 GSPS in single-channel mode. The ADC12DJ4000RF (...)
Evaluation board
TSW14J59EVM — TSW14J59 evaluation module
TSW14J59 evaluation module (EVM) is a next-generation data capture card used to evaluate the performance of the new TI JESD204C_B family of high-speed analog-to-digital converters (ADCs), high-speed digital-to-analog converters (DACs) and analog front ends (AFEs).
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Evaluation board
ANNAP-3P-WWDM60 — Annapolis Microsystems 4-channel ADC, 2-channel DAC FPGA mezzanine card up to 10GSPS
This high performance WILD FMC+ DM60 ADC & DAC has two input bandwidth options, internal sample clock options and internal 10MHz reference clock options. The WWDM60 has a choice of speed grades that utilize the ADC12DJ2700, ADC12DJ3200 and ADC12DJ5200RF up to 10GSPS. It allows for ADC and DAC (...)
From: Annapolis Micro Systems
Firmware
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Supported products & hardware
Products
High-speed DACs (>10 MSPS)
High-speed ADCs (≥10 MSPS)
RF transceivers
RF transmitters
GUI for evaluation module (EVM)
DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.20
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
Supported products & hardware
Products
High-speed DACs (>10 MSPS)
High-speed ADCs (≥10 MSPS)
Ultrasound AFEs
RF transceivers
RF receivers
RF transmitters
Hardware development
Evaluation board
Software
Support software
Simulation model
ADC12DJ5200RF IBIS and IBIS-AMI Model (Rev. A)
SLVMD65A.ZIP (49879 KB) - IBIS-AMI Model
Calculation tool
FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
Supported products & hardware
Products
High-speed ADCs (≥10 MSPS)
RF transceivers
RF receivers
Design tool
SLVRBH0 — ADC12DJ5200RF-EVM Assembly Package
Supported products & hardware
Products
High-speed ADCs (≥10 MSPS)
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs
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This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
Reference designs
TIDA-01028 — 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
Reference designs
TIDA-010128 — Scalable 20.8 GSPS reference design for 12 bit digitizers
This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
| FCCSP (ZEG) | 144 | Ultra Librarian |
Ordering & quality
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