Active analog-to-digital (ADC) front ends using a fully differential amplifier (FDA) can offer a host of advantages, such as better impedance matching, pass-band flatness and signal gain. However, if you require only a portion of the ADC’s band for your next design, it might be necessary to use an anti-aliasing filter (AAF) between the output of the FDA and the input of the ADC. An AAF will yield better signal-to-noise (SNR) performance and lower spurious or spurious-free dynamic range (SFDR) within your frequency band requirements.

With any kind of AAF filter constructions, you will have several trade-offs to consider during the implementation process: filter order and topology, or whether you will need back termination or series resistances to enhance the interface between the FDA and the ADC. In this paper, I’ll discuss these AAF nuances and how to circumvent any huddles you might encounter in your next design.

Assuming that you have decided on the correct FDA for your application and whether to use either a low-pass or band-pass filter in order to achieve optimum performance (bandwidth, SNR and SFDR) in front of the ADC, follow these three steps:

1. Understand the amplifier’s characterized load impedance (RL). In order for the amplifier to perform at its best, the amplifier should “see” the correct DC load or RL listed in the data sheet for optimum performance. This is the characterized impedance typically found at the top of the specification tables.
2. Determine a starting point for the correct amount of output series resistance to use closest to the amplifier’s outputs. This helps prevent unwanted peaking in the pass band. You’ll also typically find this information in the FDA’s data sheet - LMH5401 8-GHz, Low-Noise, Low-Power, Fully-Differential Amplifier Data Sheet.
3. Determine whether to use one or more external parallel resistors to back-terminate the input to the ADC, and the starting value of the input series resistance to isolate the ADC from the filter. These series resistors also help reduce unnecessary peaking in the pass band and “kickback” commonly found in unbuffered ADCs.

Figure 1 shows an example of the specification table.

The generalized circuit shown in Figure 2 and filter parameter list in Table 1 apply to most high-speed differential FDA and ADC interfaces; you can use both as a basis for the AAF design.

Although not every filter construction will be exactly the same, Figure 2 can serve as a blueprint on how to kick-start your design. Using this design approach will tend to minimize the insertion loss of the filter by taking advantage of the relatively high input impedance of most high-speed ADCs and the relatively low output impedance of the driving source (the FDA).

The basic AAF design process and guidelines are:

1. Set the external ADC termination resistor (R_TADC) appropriately. This helps the AAF realize a “real” impedance over its desired frequency response.
2. Select R_KB based on experience or the ADC data sheet recommendations; typically, this will be between 5Ω and 50Ω.
3. Use Equation 1 to calculate the filter load impedance so that the aggregate parallel and series combination of R_TADC, R_KB and R_ADC is between 100Ω and 400Ω. See my recommendation in the previous section.
   Equation 1. Z_AAFL - R_TADC || (R_ADC + 2R_KB)
4. Select the amplifier external series resistor (R_A). This is typically between 5Ω and 50Ω. R_A helps dampen the amplifier output response and reduce unnecessary peaking in the pass band.
5. Use the calculated Z_AAFL so that the total load seen by the amplifier (Z_AL) is optimal for the particular differential amplifier chosen. See Step No. 1 above in the AAF Design Approach Section and use Equation 2:
   Equation 2. Z_AL = 2R_A + Z_AAFL

   Keep in mind that ZAL is the FDA’s characterized _RL; therefore, using too high or too low a value can have an adverse effect on the amplifier’s linearity.

6. Calculate the filter source resistance using Equation 3:
   Equation 3. Z_AAFS = Z_O + 2R_A
7. Using a filter design program, design the filter using the same source and load impedances, if possible, Z_AAFS and Z_AAFL. This helps reduce the amount of loss in the filter. Any mismatch between the input/output impedance has a loss of 10*log(input Z/output Z). For example, with an input impedance of 50Ω and an output impedance of 200Ω, the loss of the filter is –6.0dB or 10*log(50/200). Also, using a bandwidth that is about 10% more or higher than the desired bandwidth of the application will ensure that the intended bandwidth is covered per the application, and help overcome any second- and third-order parasitic losses unrealized during the filter implementation process.

   After running a few preliminary simulations, give the circuit a quick review for the following items:

8. The value of C_{AAF2 & 3} should be sufficiently big relative to C_ADC, which minimizes the sensitivity of the filter to variations in C_ADC.
9. The ratio of Z_AAFL to Z_AAFS should not be more than 6-to-7, so that the filter is within the limits of most filter tables and design programs. Ideally, they should be the same to minimize loss, but this is not usually possible.
10. Try to use a value of C_AAF2 in the few picofarads range to minimize sensitivity to parasitic capacitance and component variations.
11. Inductors L_AAF1 and L_AAF2 should be reasonable values and in the nanohenries range.
12. The value of C_AFF2 and L_AAF2 should be reasonable values; select these two parameters to optimize the filter’s center frequency. Sometimes circuit simulators can make these values too low or too high. To make these values more reasonable, simply ratio these values with better standard-value components that maintain the same resonant frequency.
13. Use 0201 package styles if possible when designing in the gigahertz range to minimize second- and third-order parasitic effects that could disrupt the filter character shape or outline.

In some cases, the filter design program may provide more than one unique solution, especially with higher-order filters. Always choose the solution that uses the most reasonable set of component values. For filter configurations that end with a shunt capacitor, take the ADC’s internal input capacitance into consideration as well. You may need an iteration or two to set the filter pole and ultimate bandwidth correctly.