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High-speed ADCs (≥10 MSPS)

ADS42JB49

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Dual-Channel, 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS42JB49

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2.5 Power consumption (typ) (mW) 1700 Architecture Pipeline SNR (dB) 75 ENOB (bit) 12 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2.5 Power consumption (typ) (mW) 1700 Architecture Pipeline SNR (dB) 75 ENOB (bit) 12 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RGC) 64 81 mm² 9 x 9
  • Dual-Channel ADCs
  • 14- and 16-Bit Resolution
  • Maximum Clock Rate: 250 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two and Four Lanes Support
  • Analog Input Buffer with High-Impedance Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm VQFN-64
  • Power Dissipation: 850 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 73.3 dBFS
      • SFDR: 93 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.7 dBFS
      • SFDR: 89 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3
  • Dual-Channel ADCs
  • 14- and 16-Bit Resolution
  • Maximum Clock Rate: 250 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two and Four Lanes Support
  • Analog Input Buffer with High-Impedance Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm VQFN-64
  • Power Dissipation: 850 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 73.3 dBFS
      • SFDR: 93 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.7 dBFS
      • SFDR: 89 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

For all available packages, see the orderable addendum at the end of the datasheet.

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

For all available packages, see the orderable addendum at the end of the datasheet.

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Technical documentation

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Type Title Date
* Data sheet ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters datasheet (Rev. F) PDF | HTML 22 Dec 2014
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
EVM User's guide ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation Module User's Guide (Rev. D) 08 Feb 2017
Application note Correcting the Low-Frequency Response of the ADS42LBxx, ADS42JBxx for Time-Domai 02 May 2016
User guide TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) PDF | HTML 11 Jan 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 19 Mar 2015
User guide Interoperability of TI ADS42JB69 Family of JESD204B ADCs with Altera FPGAs 04 Oct 2013
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note LMK04828 as a Clock Source for the ADS42JB69 14 Nov 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS42JB49EVM — ADS42JB49 Dual-Channel, 14-Bit, 250-MSPS Analog-to-Digital Converter Evaluation Module

The ADS42JB49EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS42JB49 and LMK04828 clock jitter cleaner. The ADS42JB49 is a low power, 14-bit, 250-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

User guide: PDF
Not available on TI.com
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
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Simulation model

ADS42JB49 IBIS Model

SLAM191.ZIP (174 KB) - IBIS Model
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Schematic

ADS42JBx9EVM Design Package- Board Rev C

SLRR006.ZIP (9208 KB)
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Package Pins CAD symbols, footprints & 3D models
VQFN (RGC) 64 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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