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ADS54J42

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Dual-Channel, 14-Bit, 625-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS54J42

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 625 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 1940 Architecture Pipeline SNR (dB) 71.8 ENOB (bit) 11.6 SFDR (dB) 93 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 625 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 1940 Architecture Pipeline SNR (dB) 71.8 ENOB (bit) 11.6 SFDR (dB) 93 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 14-Bit Resolution, Dual-Chanel, 625-MSPS ADC
  • Noise Floor: –157 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 71.0 dBFS
    • NSD: –155.9 dBFS/Hz
    • SFDR: 85 dBc
    • SFDR: 93 dBc (Except HD2, HD3, and Interleaving Tones)
  • Spectral Performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 69 dBFS
    • NSD: –153.9 dBFS/Hz
    • SFDR: 76 dBc
    • SFDR: 90 dBc (Except HD2, HD3, and Interleaving Tones)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Wideband DDC Block
  • JESD204B Interface with Subclass 1 Support:
    • 2 Lanes per ADC at 6.25 Gbps
    • 4 Lanes per ADC at 3.125 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 970 mW/Ch at 625 MSPS
  • Package: 72-Pin VQFNP (10 mm × 10 mm)
  • 14-Bit Resolution, Dual-Chanel, 625-MSPS ADC
  • Noise Floor: –157 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 71.0 dBFS
    • NSD: –155.9 dBFS/Hz
    • SFDR: 85 dBc
    • SFDR: 93 dBc (Except HD2, HD3, and Interleaving Tones)
  • Spectral Performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 69 dBFS
    • NSD: –153.9 dBFS/Hz
    • SFDR: 76 dBc
    • SFDR: 90 dBc (Except HD2, HD3, and Interleaving Tones)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Wideband DDC Block
  • JESD204B Interface with Subclass 1 Support:
    • 2 Lanes per ADC at 6.25 Gbps
    • 4 Lanes per ADC at 3.125 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 970 mW/Ch at 625 MSPS
  • Package: 72-Pin VQFNP (10 mm × 10 mm)

The ADS54J42 is a low-power, wide-bandwidth, 14-bit, 625-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 6.25 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J42 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

The ADS54J42 is a low-power, wide-bandwidth, 14-bit, 625-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 6.25 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J42 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.
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* Data sheet ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter datasheet (Rev. A) PDF | HTML 31 Mar 2016

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Firmware

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ADS54J42 IBIS Model

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ADS54J42 IBIS-AMI Model

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFNP (RMP) 72 Ultra Librarian
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