ADS5292
- Maximum Sample Rate: 80 MSPS/12-Bit
- High Signal-to-Noise Ratio
- 70-dBFS SNR at 5 MHz/80 MSPS
- 71.5-dBFS SNR at 5 MHz/80 MSPS and Decimation Filter = 2
- 85-dBc SFDR at 5 MHz/80 MSPS
- Low Power Consumption
- 48 mW/CH at 50 MSPS
- 54 mW/CH at 65 MSPS
- 66 mW/CH at 80 MSPS (2 LVDS Wire Per Channel)
- Digital Processing Block
- Programmable FIR Decimation Filter and Oversampling to Minimize
Harmonic Interference - Programmable IIR High Pass Filter to Minimize DC Offset
- Programmable Digital Gain: 0 dB to 12 dB
- 2- or 4-=Channel Averaging
- Programmable FIR Decimation Filter and Oversampling to Minimize
- Flexible Serialized LVDS Outputs:
- One or Two wires of LVDS Output Lines per Channel Depending on ADC
Sampling Rate - Programmable Mapping Between ADC Input Channels and LVDS Output
Pins-Eases Board Design - Variety of Test Patterns to Verify Data Capture by
FPGA/Receiver
- One or Two wires of LVDS Output Lines per Channel Depending on ADC
- Internal and External References
- 1.8V Operation for Low Power Consumption
- Low-Frequency Noise Suppression
- Recovery From 6-dB Overload within 1 Clock Cycle
- Package: 12-mm × 12-mm 80-Pin QFP
Using CMOS process technology and innovative circuit techniques, the ADS5292 is a low power 80MSPS 8-Channel ADC. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high performance systems.
The ADS5292 has a digital processing block that integrates several commonly used digital functions for improving system performance. It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it useful for narrow-band applications, where the filters can be used conveniently to improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR.
Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC can be output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface helps keep the serial data rate low, allowing low cost FPGA based receivers to be used even at high sample rate. A unique feature is the programmable mapping module that allows flexible mapping between the input channels and the LVDS output pins. This helps greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers.
The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. The device can be driven with external references as well.
The device is available in a 12 mm × 12 mm 80-pin QFP. It is specified over a –40°C to 85°C operating temperature range. ADS5292 is completely pin-to-pin and register compatible to ADS5294.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | Octal Channel 12-Bit, 80 MSPS and Low-Power ADC datasheet (Rev. B) | 25 Jul 2012 | |
Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 22 May 2015 | ||
EVM User's guide | ADS5292 EVM (Rev. A) | 05 Mar 2015 | ||
Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 19 Jul 2013 | ||
Application note | Understanding Serial LVDS Capture in High-Speed ADCs | 10 Jul 2013 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
ADS5292EVM — ADS5292 evaluation module
The ADS5292 evaluation module (EVM) provides a flexible environment for testing the ADS5292 under a variety of clock and input conditions. This EVM allows customers to design their own filters, populate the EVM with the corresponding components and verify the performance on the EVM itself.
SBAC120 — TIGAR Support Files
Supported products & hardware
Products
High-speed ADCs (≥10 MSPS)
RF receivers
Hardware development
Evaluation board
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
Supported products & hardware
Products
Precision op amps (Vos<1mV)
General-purpose op amps
Audio op amps
Transimpedance amplifiers
High-speed op amps (GBW ≥ 50 MHz)
Power op amps
Video amplifiers
Line drivers
Transconductance amplifiers & laser drivers
Fully differential amplifiers
Precision ADCs
Biosensing AFEs
High-speed ADCs (≥10 MSPS)
Touchscreen controllers
Difference amplifiers
Instrumentation amplifiers
Audio line receivers
Analog current-sense amplifiers
Digital power monitors
Analog current-sense amplifiers with integrated shunt resistor
Digital power monitors with integrated shunt resistor
Die & wafer services
RF receivers
RF transmitters
SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
Supported products & hardware
Products
High-speed ADCs (≥10 MSPS)
RF receivers
Hardware development
Evaluation board
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
HTQFP (PFP) | 80 | Ultra Librarian |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
- Fab location
- Assembly location
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Support & training
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