All trademarks are the property of their respective owners.
The ADS5232 is a dual, high-speed, high dynamic range, 12-bit pipelined analog-to-digital converter (ADC). This converter includes a high-bandwidth sample-and-hold amplifier that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of the sample-and-hold amplifier and ADC circuitry minimizes even-order harmonics and gives excellent common-mode noise immunity.
The ADS5232 provides for setting the full-scale range of the converter without any external reference circuitry. The internal reference can be disabled, allowing low-drive, external references to be used for improved tracking in multichannel systems.
The ADS5232 provides an over-range indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front-end gain control circuitry. There is also an output enable pin to allow for multiplexing and testing on a PC board.
The ADS5232 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS5232 is available in a TQFP-64 package.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Dual, 12-Bit, 65MSPS, +3.3V Analog-to-Digital Converter datasheet (Rev. A) | 28 Mar 2006 | |
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 22 May 2015 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 19 Jul 2013 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 10 Sep 2010 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 28 Apr 2009 | ||
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 04 Sep 2008 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08 Jun 2008 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 02 Jun 2008 | ||
| EVM User's guide | ADS5231/32/37 EVM (Rev. B) | 14 Nov 2007 | ||
| EVM User's guide | ADS5231/32EVM User's Guide (Rev. A) | 26 Jun 2007 |
For additional terms or required resources, click any title below to view the detail page where available.
The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.
Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TQFP (PAG) | 64 | Ultra Librarian |
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.
Analog Engineer's Calc Installer
General calculator tool for analog design support.