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High-speed ADCs (≥10 MSPS)

ADS54J64

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Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling Analog-to-Digital Converter (ADC)

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Data sheet

ADS54J64

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 500, 1000 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 1000 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 2500 Architecture Pipeline SNR (dB) 69 ENOB (bit) 11.6 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500, 1000 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 1000 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 2500 Architecture Pipeline SNR (dB) 69 ENOB (bit) 11.6 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • Quad Channel, 14-Bit Resolution
  • Maximum Sampling Rate: 1 GSPS
  • Maximum Output Sample Rate: 500 MSPS
  • High-Impedance Analog Input Buffer
  • Analog Input Bandwidth (–3 dB): 1 GHz
  • Output Options:
    • Digital Down Conversion (DDC) Using 16-Bit NCO
    • DDC Bypass With Full Rate Output Up to 500 MSPS
  • Differential Full-Scale Input: 1.1 VPP
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • Spectral Performance:
    • fIN = 190-MHz IF at –1 dBFS:
      • SNR: 69 dBFS
      • NSD: –153 dBFS/Hz
      • SFDR: 86 dBc (HD2, HD3),
        95 dBFS (Non HD2, HD3)
    • fIN = 370-MHz IF at –3 dBFS:
      • SNR: 68.5 dBFS
      • NSD: –152.5 dBFS/Hz
      • SFDR: 80 dBc (HD2, HD3),
        86 dBFS (Non HD2, HD3)
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Power Consumption: 625 mW/Ch, 2.5 W Total
  • Power Supplies: 1.15 V, 1.15 V, 1.9 V
  • Quad Channel, 14-Bit Resolution
  • Maximum Sampling Rate: 1 GSPS
  • Maximum Output Sample Rate: 500 MSPS
  • High-Impedance Analog Input Buffer
  • Analog Input Bandwidth (–3 dB): 1 GHz
  • Output Options:
    • Digital Down Conversion (DDC) Using 16-Bit NCO
    • DDC Bypass With Full Rate Output Up to 500 MSPS
  • Differential Full-Scale Input: 1.1 VPP
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • Spectral Performance:
    • fIN = 190-MHz IF at –1 dBFS:
      • SNR: 69 dBFS
      • NSD: –153 dBFS/Hz
      • SFDR: 86 dBc (HD2, HD3),
        95 dBFS (Non HD2, HD3)
    • fIN = 370-MHz IF at –3 dBFS:
      • SNR: 68.5 dBFS
      • NSD: –152.5 dBFS/Hz
      • SFDR: 80 dBc (HD2, HD3),
        86 dBFS (Non HD2, HD3)
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Power Consumption: 625 mW/Ch, 2.5 W Total
  • Power Supplies: 1.15 V, 1.15 V, 1.9 V

The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode.

A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode.

A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.
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* Data sheet ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x Oversampling, Analog-to-Digital Converter datasheet PDF | HTML 09 Oct 2017
EVM User's guide ADS54J64 Evaluation Module User's Guide 15 Sep 2017

Design & development

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Evaluation board

ADS54J64EVM — ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling ADC Evaluation Module

The ADS54J64 evaluation module (EVM) is used to evaluate the ADS54J64 quad-channel, 14-bit, 1-GSPS, 2x-oversampling analog-to-digital converter (ADC). The EVM has transformer-coupled analog inputs to accommodate a wide range of signal sources and frequencies. The EVM is designed to connect (...)

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Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
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Simulation model

ADS54J64 IBIS Model

SBAM345.ZIP (38 KB) - IBIS Model
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Simulation model

ADS54J64 IBIS-AMI Model

SBAM344.ZIP (2273 KB) - IBIS-AMI Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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