TSW14J59EVM

TSW14J59 evaluation module

TSW14J59EVM

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Overview

TSW14J59 evaluation module (EVM) is a next-generation data capture card used to evaluate the performance of the new TI JESD204C_B family of high-speed analog-to-digital converters (ADCs), high-speed digital-to-analog converters (DACs) and analog front ends (AFEs).

Populated with Kintex Ultrascale+® FPGA and using JESD204B/C IP solutions, the TSW14J59 can be dynamically configured to support all lane speeds from 1 Gbps to 32 Gbps - from 1 to 16 lanes.

Together with the accompanying High-Speed Data Converter Pro (HSDC Pro) data capture analysis & software program, it is a complete system that captures and evaluates data samples from ADC, DAC and AFE EVMs that use JESD204B and/or JESD204C.

Features
  • Quickly evaluate JESD204B and JESD204C ADC, DAC or AFE performance using TI HSDC Pro software
  • Direct connection to all TI JESD204B and JESD204C EVMs using an FMC+ standard connector (backwards compatible to FMC-equipped EVMs)
  • JESD204B and JESD204C RX and TX IP cores with 16 routed transceiver channels; operating range from 1 Gbps to 32 Gbps
  • Support for SUBCLASS 0, 1 and 2 operation   
  • 24-Gb DDR4 SDRAM (split into two banks each of 3 independent 256 × 16, 4-Gb SDRAMs; total of 1.536 G 16-bit samples)
High-speed ADCs (≥10 MSPS)
ADC12DJ5200RF RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS
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Evaluation board

TSW14J59EVM — Data capture/pattern generator: data converter EVM with 16 JESD204B/C lanes from 1.6-24.5 Gbps USB-C

Design tool

TSW14J59EVM Design Files — SLWR042.ZIP (19172KB)

TI's Standard Terms and Conditions for Evaluation Items apply.

Technical documentation

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Type Title Date
EVM User's guide TSW14J59EVM JESD204C Data Capture and Pattern Generator Card User's Guide PDF | HTML 11 Apr 2023
Certificate TSW14J59EVM EU RoHS Declaration of Conformity (DoC) 04 Apr 2023

Support & training

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