The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD observation receiver.
The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS58J63 | VQFN (72) | 10.00 mm x 10.00 mm |
Changes from * Revision (June 2015) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
INPUT/REFERENCE | |||
INAP/M | 42, 41 | I | Differential analog input for channel A |
INBP/M | 36, 37 | I | Differential analog input for channel B |
INCP/M | 19, 18 | I | Differential analog input for channel C |
INDP/M | 13, 14 | I | Differential analog input for channel D |
CLOCK/SYNC | |||
CLKINP/M | 27, 28 | I | Differential clock input for ADC |
SYSREFP/M | 33, 34 | I | External sync input |
CONTROL/SERIAL | |||
RESET | 48 | I | Hardware reset. Active high. This pin has an internal 150-kΩ pull-down resistor. |
SCLK | 6 | I | Serial interface clock input |
SDIN | 5 | I | Serial interface data input. |
SEN | 7 | I | Serial interface enable |
SDOUT | 11 | O | Serial interface data output. |
PDN | 50 | I/O | Power down. Can be configured via SPI register setting. |
RES | 49 | – | Reserve Pin. Connect to GND |
NC | 22, 23 | – | No connect |
TRDYAB | 54 | O | Trigger ready output for burst mode for channel A,B. Can be configured via SPI to TRDY signal for all four channels in burst mode. Can be left open if not used. |
TRIGAB | 53 | I | Manual burst mode trigger input channel A,B. Can be configured via SPI to manual trigger input signal for all four channels in burst mode. Can be connected to GND if not used. |
TRDYCD | 1 | O | Trigger ready output for burst mode for channel C,D. Can be configured via SPI to TRDY signal for all four channels in burst mode. Can be left open if not used. |
TRIGCD | 2 | I | Manual burst mode trigger input channel C,D. Can be configured via SPI to manual trigger input signal for all four channels in burst mode. Can be connected to GND if not used. |
DATA INTERFACE | |||
DAP/M | 58, 59 | O | JESD204B Serial data output for channel A |
DBP/M | 61, 62 | O | JESD204B Serial data output for channel B |
DCP/M | 66, 65 | O | JESD204B Serial data output for channel C |
DDP/M | 69, 68 | O | JESD204B Serial data output for channel D |
SYNCbABP/M | 55, 56 | I | Synchronization input for JESD204B port channel A,B. Can be configured via SPI to SYNCb signal for all four channels. Needs external termination. |
SYNCbCDP/M | 72, 71 | I | Synchronization input for JESD204B port channel C,D. Can be configured via SPI to SYNCb signal for all four channels. Needs external termination. |
POWER SUPPLY | |||
AVDD3V | 10, 16, 24, 31, 39, 45 | I | Analog 3 V for analog buffer |
AVDD | 9, 12, 15, 17, 20, 25, 30, 35, 38, 40, 43, 44, 46 | I | Analog 1.9-V power supply |
DVDD | 8, 47 | I | Digital 1.9-V power supply |
IOVDD | 4, 51, 57, 64, 70 | I | Digital 1.15-V power supply for the JESD204B transmitter |
AGND | 21, 26, 29, 32 | I | Analog ground |
DGND | 3, 52, 60, 63, 67 | I | Digital ground |