SBASAL3A September 2024 – January 2025 ADC3668 , ADC3669
PRODUCTION DATA
The ADC366x includes a time-stamp feature which enables tagging a specific sample on the analog input in DDC bypass mode. When enabling the feature (via SPI write), a logic low-to-high transition on the GPIO/SYSREF pin is registered on the rising edge of the sampling clock. The time stamp signal is output on the lane DOUT0 (LSB); however, the signal is not latency matched with the output data.
As shown in Figure 8-19 the time stamp signal is indicated 35 clock cycles ahead of the output data:
ADDR | DATA | DESCRIPTION |
---|---|---|
0x146 | 0x00 | Enable SYSREF on pin GPIO0. |
0x162 | 0xC0 | Enable time stamp function replacing the LSB. |