SBASAL3 September   2024 ADC3669

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (ADC3668 - 250 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (ADC3669 - 500 MSPS)
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics, ADC3668
    11. 5.11 Typical Characteristics, ADC3669
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Nyquist Zone Selection
        2. 7.3.1.2 Analog Front End Design
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 Multi-Chip Synchronization
        1. 7.3.3.1 SYSREF Monitor
      4. 7.3.4 Time-Stamp
      5. 7.3.5 Overrange
      6. 7.3.6 External Voltage Reference
      7. 7.3.7 Digital Gain
      8. 7.3.8 Decimation Filter
        1. 7.3.8.1 Uncommon Decimation Ratios
        2. 7.3.8.2 Decimation Filter Response
        3. 7.3.8.3 Decimation Filter Configuration
        4. 7.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 7.3.9 Digital Interface
        1. 7.3.9.1 Parallel LVDS (DDR)
        2. 7.3.9.2 Serial LVDS (SLVDS) with Decimation
        3. 7.3.9.3 Output Data Format
        4. 7.3.9.4 32-bit Output Resolution
        5. 7.3.9.5 Output MUX
        6. 7.3.9.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Digital Channel Averaging
      3. 7.4.3 Power Down Mode
    5. 7.5 Programming
      1. 7.5.1 GPIO Programming
      2. 7.5.2 Register Write
      3. 7.5.3 Register Read
      4. 7.5.4 Device Programming
      5. 7.5.5 Register Map
      6. 7.5.6 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband Spectrum Analyzer
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Initialization Set Up
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Sampling Clock Input

The sampling clock input is designed to be driven differentially with external AC coupling and termination. The ADC provides internal common mode voltage biasing as shown in Figure 7-7.

ADC3668 ADC3669 Sampling Clock Input CircuitryFigure 7-7 Sampling Clock Input Circuitry

The internal sampling clock path was designed for low residual phase noise contribution. The sampling clock circuitry requires a dedicated, low noise power supply for best phase noise and jitter performance. The internal residual clock phase noise is also sensitive to clock amplitude.

The internal residual clock noise consists of two components: 1) phase noise and 2) amplitude noise as shown in Table 7-1. The phase noise scales with input frequency and sampling rate (20*log(fIN/FS)) while the amplitude noise does not scale.

Table 7-1 Phase and Amplitude Noise at FS = 500MHz
Frequency Offset (MHz)Phase Noise (dBc/Hz)Amplitude Noise (dBc/Hz)
0.001−130−129
0.01−140−139
0.1−150−149
1−160−159
3−165−164
10−165−164

Figure 7-8 and Figure 7-9 show the phase and amplitude noise at three different input frequencies.

ADC3668 ADC3669 Phase Noise ExamplesFigure 7-8 Phase Noise Examples
ADC3668 ADC3669 Amplitude Noise ExamplesFigure 7-9 Amplitude Noise Examples

The internal clock noise is also dependent on the external clock amplitude. Figure 7-10 to Figure 7-13 show the expected AC performance for different input frequencies across clock amplitude.

ADC3668 ADC3669 AC vs Clock AmplitudeFS = 500MSPS, FIN = 100MHz, AIN = −1dBFSFigure 7-10 AC vs Clock Amplitude
FS = 500MSPS, FIN = 100MHz, AIN = −1dBFS
ADC3668 ADC3669 AC vs Clock AmplitudeFS = 250MSPS, FIN = 100MHz, AIN = −1dBFSFigure 7-12 AC vs Clock Amplitude
FS = 250MSPS, FIN = 100MHz, AIN = −1dBFS
ADC3668 ADC3669 AC vs Clock AmplitudeFS = 500MSPS, FIN = 400MHz, AIN = −1dBFSFigure 7-11 AC vs Clock Amplitude
FS = 500MSPS, FIN = 400MHz, AIN = −1dBFS
ADC3668 ADC3669 AC vs Clock AmplitudeFS = 250MSPS, FIN = 240MHz, AIN = −1dBFSFigure 7-13 AC vs Clock Amplitude
FS = 250MSPS, FIN = 240MHz, AIN = −1dBFS