SBASAL3 September   2024 ADC3669

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (ADC3668 - 250 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (ADC3669 - 500 MSPS)
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics, ADC3668
    11. 5.11 Typical Characteristics, ADC3669
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Nyquist Zone Selection
        2. 7.3.1.2 Analog Front End Design
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 Multi-Chip Synchronization
        1. 7.3.3.1 SYSREF Monitor
      4. 7.3.4 Time-Stamp
      5. 7.3.5 Overrange
      6. 7.3.6 External Voltage Reference
      7. 7.3.7 Digital Gain
      8. 7.3.8 Decimation Filter
        1. 7.3.8.1 Uncommon Decimation Ratios
        2. 7.3.8.2 Decimation Filter Response
        3. 7.3.8.3 Decimation Filter Configuration
        4. 7.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 7.3.9 Digital Interface
        1. 7.3.9.1 Parallel LVDS (DDR)
        2. 7.3.9.2 Serial LVDS (SLVDS) with Decimation
        3. 7.3.9.3 Output Data Format
        4. 7.3.9.4 32-bit Output Resolution
        5. 7.3.9.5 Output MUX
        6. 7.3.9.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Digital Channel Averaging
      3. 7.4.3 Power Down Mode
    5. 7.5 Programming
      1. 7.5.1 GPIO Programming
      2. 7.5.2 Register Write
      3. 7.5.3 Register Read
      4. 7.5.4 Device Programming
      5. 7.5.5 Register Map
      6. 7.5.6 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband Spectrum Analyzer
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Initialization Set Up
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.9.2 Serial LVDS (SLVDS) with Decimation

When using real or complex decimation, the output data is serialized and transmitted using fewer LVDS transmitters. A frame clock (FCLK) marks the start and stop of the sample while the data bits are clocked out on the rising and falling edge of the data clock (DCLK). The frame clock is output on DOUT0 and there are a maximum number of 15 LVDS lanes available for data output. The output interface mapping always starts on lane DOUT15 unless the output mux is used.

In real decimation, only single band per ADC is supported.

The # of lanes and output data rates can be calculated with the following parameters:

  • R: Output Resolution: 16-bit = 1, 32-bit = 2
  • B: Total number of DDC bands
  • C: Real or complex decimation: real = 1, complex = 2
  • D: Decimation factor
  • FS: ADC sampling clock frequency
  • K = R x B x C
  • L = 8 x K / D (# of LVDS output lanes)
For L < 1, the DCLK output divider needs to be enabled (0x590, D1)

Table 7-10 SLVDS clock and data rate calculations
ParameterL ≥1L ˂ 1
Frame Clock (FCLK) FrequencyFS / D
Data Bit Clock (DCLK) FrequencyFSDOUT / 2
Data output rate DOUT per Lane (DOUT/L)FS x 2FS / D x 16 x K

The SLVDS frame assembly is automatically performed by the ADC and follows this scheme, starting on lane DOUT15 and with the MSB of each channel:

Table 7-11 SLVDS frame assembly
DecimationOutput ResolutionBand order
Real16-bitB0, B1
32-bit
Complex16-bitB0I, B0Q, B1I, B1Q, B2I, B2Q, B3I, B3Q
32-bit

Following details the frame assembly and calculations for four different examples.

Example 1: Dual band, real decimation by 8, 16-bit output resolution, FS = 500MSPS

  • K = 2 (R = 1, B = 2, C = 1)
  • L = 8 x K / D = 8 x 2 / 8 = 2
  • FCLK = FS / D = 500MSPS / 8 = 62.5MHz
  • DCLK = 500MHz
  • DOUT/Lane = 1Gbps

The SLVDS frame assembly for example 1 is shown in Figure 7-56. Two lanes are used to output the data with odd bits on DCLK rising edge and even bits on DCLK falling edge.

ADC3668 ADC3669 SLVDS frame assembly for example 1Figure 7-56 SLVDS frame assembly for example 1

Example 2: Dual band, real decimation by 128, 32-bit output resolution, FS = 500MSPS

  • K = 4 (R = 2, B = 2, C = 1)
  • L = 8 x K / D = 8 x 4 / 128 = 1/4 => One lane is used.
  • FCLK = FS / D = 500 MSPS / 128 = 3.91MHz
  • DCLK = 125MHz
  • DOUT/Lane = 0.25Gbps

The SLVDS frame assembly for example 2 is shown in Figure 7-57. A single lane is used to first transmit the 32 bit of DDC band 0 (B0) followed by 32 bit of DDC band 1.

ADC3668 ADC3669 SLVDS frame assembly for example 2Figure 7-57 SLVDS frame assembly for example 2

Example 3: Dual band, complex decimation by 16, 16-bit output resolution, FS = 500MSPS

  • K = 4 (R = 1, B = 2, C = 2)
  • L = 8 x K / D = 8 x 4 / 16 = 2
  • FCLK = FS / D = 500MSPS / 16 = 31.25MHz
  • DCLK = 500MHz
  • DOUT/Lane = 1Gbps

The SLVDS frame assembly for example 3 is shown in Figure 7-58. The frame assembly starts on DOUT15 with MSB of DDC band B0. Each sample is spread across 2 lanes.

ADC3668 ADC3669 SLVDS frame assembly for example 3Figure 7-58 SLVDS frame assembly for example 3

Example 4: Quad band, complex decimation by 8, 16-bit output resolution, FS = 500MSPS

  • K = 8 (R = 1, B = 4, C = 2)
  • L = 8 x K / D = 8 x 8 / 8 = 8
  • FCLK = FS / D = 500MSPS / 8 = 62.5MHz
  • DCLK = 500MHz
  • DOUT/Lane = 1Gbps

The SLVDS frame assembly for example 3 is shown in Figure 7-59. The frame assembly starts on DOUT15 with MSB of DDC band B0. Each sample is spread across 8 lanes.

ADC3668 ADC3669 SLVDS frame assembly for example 4Figure 7-59 SLVDS frame assembly for example 4

Example 5: Single band, complex decimation by 256, 32-bit output resolution, FS = 500MSPS

  • K = 8 (R = 2, B = 2, C = 2)
  • L = 8 x K / D = 8 x 8 / 256 = 1/4 => One lane is used.
  • FCLK = FS / D = 500MSPS / 256 = 1.95MHz
  • DOUT/Lane = FS / D x 16 x K = 500MSPS / 256 x 16 x 8 = 250Mbps
  • DCLK = 125MHz

The SLVDS frame assembly for example 4 is shown in Figure 7-60. The frame assembly uses only DOUT15 starting with the 32-bit 'I' sample of DDC band 0 and ending with the 32-bit 'Q' sample of DDC band 1.

ADC3668 ADC3669 SLVDS frame assembly for example 5Figure 7-60 SLVDS frame assembly for example 5