Each digital down-converter (DDC) uses a 48-bit numerically controlled oscillator (NCO) to fine tune the frequency placement prior to the digital filtering. Up to four different NCO frequencies for each DDC are programmed using SPI register writes. The digital NCOs are designed to have a SFDR of at least 100dB.

Figure 7-53 NCO Block Diagram

There are two different NCO operating modes, phase continuous and infinite phase coherent.

1. Phase Continuous NCO

   During a NCO frequency change, the NCO phase gradually adjusts to the new frequency as shown in Figure 7-54 (left). The 'dashed' line shows the phase of original f₁ frequency.

2. Infinite Phase Coherent NCO

   With a phase coherent NCO, all frequencies are synchronized to a single event using SYSREF. This enables an infinite amount of frequency hops without the need to reset the NCO as phase coherency is maintained between frequency hops. This is illustrated in Figure 7-54 (right). When returning to the original frequency f₁ the NCO phase appears as if the NCO had never changed frequencies.

Figure 7-54 Phase Continuous (left) and Infinite Phase Coherent (right) NCO Frequency Switching

The oscillator generates a complex exponential sequence of:

where: frequency (ω) is specified as a signed number by the 48-bit register setting

The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to a frequency equal to f_IN + f_NCO. The NCO frequency can be tuned from –F_S/2 to +F_S/2 and is processed as a signed, 2s complement number.

The NCO frequency setting is set by the 48-bit register value given and calculated as:

where:

• NCO = NCO register setting (decimal value)
• f_NCO = Desired NCO frequency (MHz)
• F_S = ADC sampling rate (MSPS)

The NCO programming is illustrated with this example:

• ADC sampling rate F_S = 500MSPS
• Desired NCO frequency = 120MHz

Table 7-9 shows the register writes to set frequency 0 of the NCO of DDC0 to that frequency: