SBASAB5A March 2024 – December 2024 ADC3683-SP
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The ADC3683-SP offers a flexible set of digital signal processing (DSP) features (Figure 7-10) where all or a subset of the features can be used. The ADC cores provide an 18-bit output which can be passed to the digital down converters (DDCs) or directly provided to the digital interface. Since the ADC core offers very low latency, the DSP features have to be disabled (D2 of 0x24) for the lowest latency.
Before data is sent on the data lanes, the data first passes through a resolution selection block and then an output bit mapper. The resolution selector offers selection of output resolutions: 14-bit, 16-bit, 18-bit, or 20-bit. For 14-bit and 16-bit output resolutions, the LSBs are truncated during the reformatting. Note, in 20-bit output mode, if the DDCs are not used, then two zeros are simply appended as LSBs. The output bit mapper maps each data bit to a position within the data stream for each active lane.