SBASAB5A March   2024  – December 2024 ADC3683-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter
          2. 7.3.1.2.2 AC Coupling
          3. 7.3.1.2.3 DC Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Differential Vs Single-ended Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference
      4. 7.3.4 Digital Data Path & Interface
        1. 7.3.4.1 Data Path Overview
        2. 7.3.4.2 Digital Interface
        3. 7.3.4.3 DCLKIN
        4. 7.3.4.4 Output Scrambler
        5. 7.3.4.5 Output Bit Mapper
          1. 7.3.4.5.1 2-Wire Mode
          2. 7.3.4.5.2 1-Wire Mode
          3. 7.3.4.5.3 1/2-Wire Mode
        6. 7.3.4.6 Output Data Format
        7. 7.3.4.7 Test Pattern
      5. 7.3.5 Digital Down Converter
        1. 7.3.5.1 Decimation Operation
        2. 7.3.5.2 Numerically Controlled Oscillator (NCO)
        3. 7.3.5.3 Decimation Filters
        4. 7.3.5.4 SYNC
        5. 7.3.5.5 Output Data Format with Decimation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Averaging Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Control
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
      3. 7.5.3 Device Configuration Steps
      4. 7.5.4 Register Map
        1. 7.5.4.1 Detailed Register Description
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5.3 Decimation Filters

Table 7-5 provides an overview of the passband bandwidths and output data rates of the different decimation settings with respect to the ADC sampling rate FS.

Table 7-5 Decimation Filter Summary and Maximum Available Output Bandwidth
REAL/COMPLEX DECIMATION DECIMATION SETTING N OUTPUT RATE OUTPUT BANDWIDTH OUTPUT RATE
(FS = 65 MSPS)		 OUTPUT BANDWIDTH
(FS = 65 MSPS)
Complex 2 FS / 2 complex 0.8 × FS / 2 32.5 MSPS complex 26 MHz
4 FS / 4 complex 0.8 × FS / 4 16.25 MSPS complex 13 MHz
8 FS / 8 complex 0.8 × FS / 8 8.125 MSPS complex 6.5 MHz
16 FS / 16 complex 0.8 × FS / 16 4.0625 MSPS complex 3.25 MHz
32 FS / 32 complex 0.8 × FS / 32 2.03125 MSPS complex 1.625 MHz
Real 2 FS / 2 0.4 × FS / 2 32.5 MSPS 13 MHz
4 FS / 4 0.4 × FS / 4 16.25 MSPS 6.5 MHz
8 FS / 8 0.4 × FS / 8 8.125 MSPS 3.25 MHz
16 FS / 16 0.4 × FS / 16 4.0625 MSPS 1.625 MHz
32 FS / 32 0.4 × FS / 32 2.03125 MSPS 0.8125 MHz

The decimation filter responses are normalized to the ADC sampling clock frequency FS and illustrated in Figure 7-21 to Figure 7-30. Each figure contains the filter passband, transition band(s) and stopband(s).

ADC3683-SP Decimation by 2 Filter Frequency ResponseFigure 7-21 Decimation by 2 Filter Frequency Response
ADC3683-SP Decimation by 4 Filter Frequency ResponseFigure 7-23 Decimation by 4 Filter Frequency Response
ADC3683-SP Decimation by 8 Filter Frequency ResponseFigure 7-25 Decimation by 8 Filter Frequency Response
ADC3683-SP Decimation by 16 Filter Frequency ResponseFigure 7-27 Decimation by 16 Filter Frequency Response
ADC3683-SP Decimation by 32 Filter Frequency ResponseFigure 7-29 Decimation by 32 Filter Frequency Response
ADC3683-SP Decimation by 2 Filter Passband Ripple ResponseFigure 7-22 Decimation by 2 Filter Passband Ripple Response
ADC3683-SP Decimation by 4 Filter Passband Ripple ResponseFigure 7-24 Decimation by 4 Filter Passband Ripple Response
ADC3683-SP Decimation by 8 Filter Passband Ripple ResponseFigure 7-26 Decimation by 8 Filter Passband Ripple Response
ADC3683-SP Decimation by 16 Filter Passband Ripple ResponseFigure 7-28 Decimation by 16 Filter Passband Ripple Response
ADC3683-SP Decimation by 32 Filter Passband Ripple ResponseFigure 7-30 Decimation by 32 Filter Passband Ripple Response