SBASAB5A March   2024  – December 2024 ADC3683-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter
          2. 7.3.1.2.2 AC Coupling
          3. 7.3.1.2.3 DC Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Differential Vs Single-ended Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference
      4. 7.3.4 Digital Data Path & Interface
        1. 7.3.4.1 Data Path Overview
        2. 7.3.4.2 Digital Interface
        3. 7.3.4.3 DCLKIN
        4. 7.3.4.4 Output Scrambler
        5. 7.3.4.5 Output Bit Mapper
          1. 7.3.4.5.1 2-Wire Mode
          2. 7.3.4.5.2 1-Wire Mode
          3. 7.3.4.5.3 1/2-Wire Mode
        6. 7.3.4.6 Output Data Format
        7. 7.3.4.7 Test Pattern
      5. 7.3.5 Digital Down Converter
        1. 7.3.5.1 Decimation Operation
        2. 7.3.5.2 Numerically Controlled Oscillator (NCO)
        3. 7.3.5.3 Decimation Filters
        4. 7.3.5.4 SYNC
        5. 7.3.5.5 Output Data Format with Decimation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Averaging Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Control
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
      3. 7.5.3 Device Configuration Steps
      4. 7.5.4 Register Map
        1. 7.5.4.1 Detailed Register Description
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 HBP Package, 64-Pin CFP
(Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
INPUT
AINP 21 I Positive analog input for ADC A.
AINM 22 I Negative analog input for ADC A.
BINP 60 I Positive analog input for ADC B.
BINM 59 I Negative analog input for ADC B.
CLKP 8 I Positive sampling clock input for ADCs A & B.
CLKM 9 I Negative sampling clock input for ADCs A & B.
VREF 4 I External, 1.6V, voltage reference input.
REFGND 5 I Voltage reference ground. This pin allows close placement of the decoupling capacitors near the VREF input when using either the internal reference or an external reference.
CTRL 6 I This pin is used to configure the default sampling clock type and voltage reference source upon power up (see Section 7.5.1). There is an internal 100kΩ pull-up resistor to AVDD.
PDN/SYNC 3 I Dual purpose, active high, pin. The pin can be configured to control the power down state of the device or as a synchronization input. The pin functionality can be configured via SPI (default function is PDN). This pin has an internal 21kΩ pull-down resistor.
RESET 12 I Active high hardware reset pin. This pin has an internal 21kΩ pull-down resistor.
DCLKINP 39 I Positive input for the interface clock. This pin connects to DCLKINM through an internal 100Ω termination resistor.
DCLKINM 38 I Negative input for the interface clock. This pin connects to DCLKINP through an internal 100Ω termination resistor.
OUTPUT
DA0P 29 O Positive output for interface lane A0.
DA0M 28 O Negative output for interface lane A0.
DA1P 27 O Positive output for interface lane A1.
DA1M 26 O Negative output for interface lane A1.
DB0P 52 O Positive output for interface lane B0.
DB0M 53 O Negative output for interface lane B0.
DB1P 54 O Positive output for interface lane B1.
DB1M 55 O Negative output for interface lane B1.
DCLKP 37 O Positive output of the interface clock.
DCLKM 36 O Negative output of the interface clock.
FCLKP 42 O Positive output of the interface frame clock.
FCLKM 43 O Negative output of the interface frame clock.
VCM 11 O Common-mode output voltage of the analog inputs (typically 0.95V).
SPI
SEN 25 I Active low SPI enable. This pin has an internal 21kΩ pull-up resistor to AVDD.
SCLK 56 I SPI clock input. This pin has an internal 21kΩ pull-down resistor.
SDIO 13 I/O SPI data input or output. This pin has an internal 21kΩ pull-down resistor.
POWER
AVDD 7, 24, 57 I Analog supply input, 1.8V.
GND 20, 23, 58, 61 I Ground supply input, 0V.
IOVDD 35, 44 I Interface supply input, 1.8V.
IOGND 40 I Interface ground supply input, 0V.
OTHER
DAP DAP - Die attached pad (thermal pad), connect to GND.
NC 1, 2, 10, 14, 15, 16, 17, 18, 19, 30, 31, 32, 33, 34, 41, 45, 46, 47, 48, 49, 50, 51, 62, 63, 64 - No connect pins. Connect to ground or leave floating.(1)
(1) Thermal pad and top metal lid are connected to pin 17. Can be grounded or no connect.