SBASAB5 March 2024 ADC3683-SP
PRODMIX
Refer to the PDF data sheet for device specific package drawings
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
INPUT/REFERENCE | |||
AINP | 21 | I | Positive analog input, channel A |
AINM | 22 | I | Negative analog input, channel A |
BINP | 60 | I | Positive analog input, channel B |
BINM | 59 | I | Negative analog input, channel B |
REFBUF | 6 | I | 1.2V external voltage reference input for use with internal reference buffer. Internal 100kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions. |
REFGND | 5 | I | Reference ground input |
VCM | 11 | O | Common-mode voltage output for the analog inputs, 0.95V |
VREF | 4 | I | External voltage reference input, 1.6V |
CLOCK | |||
CLKP | 8 | I | Positive differential sampling clock input for the ADC |
CLKM | 9 | I | Negative differential sampling clock input for the ADC |
CONFIGURATION | |||
NC | 1, 2, 10, 14, 15, 16, 17, 18, 19, 30, 31, 32, 33, 34, 41, 45, 46, 47, 48, 49, 50, 51, 62, 63, 64 | - | Unbonded pins. Connect to ground or leave floating.(1) |
PDN/SYNC | 3 | I | Power down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21kΩ pull-down resistor. |
RESET | 12 | I | Hardware reset. Active high. This pin has an internal 21kΩ pull-down resistor. |
SEN | 25 | I | Serial interface enable. Active low. This pin has an internal 21kΩ pull-up resistor to AVDD. |
SCLK | 56 | I | Serial interface clock input. This pin has an internal 21kΩ pull-down resistor. |
SDIO | 13 | I/O | Serial interface data input and output. This pin has an internal 21kΩ pull-down resistor. |
DIGITAL INTERFACE | |||
DA0P | 29 | O | Positive differential serial LVDS output for lane 0, channel A |
DA0M | 28 | O | Negative differential serial LVDS output for lane 0, channel A |
DA1P | 27 | O | Positive differential serial LVDS output for lane 1, channel A |
DA1M | 26 | O | Negative differential serial LVDS output for lane 1, channel A |
DB0P | 52 | O | Positive differential serial LVDS output for lane 0, channel B |
DB0M | 53 | O | Negative differential serial LVDS output for lane 0, channel B |
DB1P | 54 | O | Positive differential serial LVDS output for lane 1, channel B |
DB1M | 55 | O | Negative differential serial LVDS output for lane 1, channel B |
DCLKP | 37 | O | Positive differential serial LVDS bit clock output. |
DCLKM | 36 | O | Negative differential serial LVDS bit clock output. |
DCLKINP | 39 | I | Positive differential serial LVDS bit clock input. Internal 100Ω differential termination. |
DCLKINM | 38 | I | Negative differential serial LVDS bit clock input. Internal 100Ω differential termination. |
FCLKP | 42 | O | Positive differential serial LVDS frame clock output. |
FCLKM | 43 | O | Negative differential serial LVDS frame clock output. |
POWER SUPPLY | |||
AVDD | 7, 24, 57 | I | Analog 1.8V power supply |
GND | 20, 23, 58, 61 | I | Ground, 0V |
IOVDD | 35, 44 | I | 1.8V power supply for digital interface |
IOGND | 40 | I | Ground, 0V for digital interface |
DAP | DAP | - | Die attached pad (thermal pad), connect to GND. |