SBASAB5 March 2024 ADC3683-SP
PRODMIX
Refer to the PDF data sheet for device specific package drawings
To maximize the ADC SNR performance, the external sampling clock should be low jitter and differential signaling with a high slew rate. This is especially important in IF sampling applications (Figure 7-10 and Figure 7-11). For less jitter sensitive applications, the device provides the option to operate with single ended signaling which saves additional power consumption.