SBASAB5A March   2024  – December 2024 ADC3683-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter
          2. 7.3.1.2.2 AC Coupling
          3. 7.3.1.2.3 DC Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Differential Vs Single-ended Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference
      4. 7.3.4 Digital Data Path & Interface
        1. 7.3.4.1 Data Path Overview
        2. 7.3.4.2 Digital Interface
        3. 7.3.4.3 DCLKIN
        4. 7.3.4.4 Output Scrambler
        5. 7.3.4.5 Output Bit Mapper
          1. 7.3.4.5.1 2-Wire Mode
          2. 7.3.4.5.2 1-Wire Mode
          3. 7.3.4.5.3 1/2-Wire Mode
        6. 7.3.4.6 Output Data Format
        7. 7.3.4.7 Test Pattern
      5. 7.3.5 Digital Down Converter
        1. 7.3.5.1 Decimation Operation
        2. 7.3.5.2 Numerically Controlled Oscillator (NCO)
        3. 7.3.5.3 Decimation Filters
        4. 7.3.5.4 SYNC
        5. 7.3.5.5 Output Data Format with Decimation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Averaging Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Control
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
      3. 7.5.3 Device Configuration Steps
      4. 7.5.4 Register Map
        1. 7.5.4.1 Detailed Register Description
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4.2 Digital Interface

Table 7-2 provides an overview for the resulting serialization factor depending on output resolution and interface mode. The output serialization factor is internally adjusted based on the interface mode setting and resolution; however, the maximum SLVDS interface output data rate of 1Gbps can not be exceeded regardless of the interface settings. Note, the DCLKIN frequency needs to be adjusted accordingly as well. For example, changing the output resolution from 18-bit to 16-bit in 2-wire mode results in DCLKIN equaling FS * 4 instead of FS * 4.5.

The programming sequence for changing the output interface and/or resolution is shown in Section 7.5.3.

Note: When possible, interface modes that allow for an integer ratio between the DCLKIN frequency and the sample clock (CLK) frequency are recommended. This eases meeting the DCLKIN to CLK timing requirements described in Section 7.3.4.3.
Note: Since the ADC3683-SP SNR is very high, the LVDS outputs can potentially couple and degrade the SNR. Therefore, a half swing LVDS mode is provided to reduce the LVDS output swing and minimize coupling. When possible, enable half swing (D6 of 0x1A) to minimize degrading the ADC SNR.
Table 7-2 Digital Interface Modes
Output Resolution Interface Serialization Factor FCLK DCLKIN DCLK Data Rate
14-bit 2-Wire 7x FS/2 FS* 3.5 FS* 3.5 FS* 7
1-Wire 14x FS FS* 7 FS* 7 FS* 14
1/2-Wire 28x FS FS* 14 FS* 14 FS* 28
16-bit 2-Wire 8x FS/2 FS* 4 FS* 4 FS* 8
1-Wire 16x FS FS* 8 FS* 8 FS* 16
1/2-Wire 32x FS FS* 16 FS* 16 FS* 32
18-bit 2-Wire 9x FS/2 FS* 4.5 FS* 4.5 FS* 9
1-Wire 18x FS FS* 9 FS* 9 FS* 18
1/2-Wire 36x FS FS* 18 FS* 18 FS* 36
20-bit 2-Wire 10x FS/2 FS* 5 FS* 5 FS* 10
1-Wire 20x FS FS* 10 FS* 10 FS* 20
1/2-Wire 40x FS FS* 20 FS* 20 FS* 40