SBASAB5 March 2024 ADC3683-SP
PRODMIX
Refer to the PDF data sheet for device specific package drawings
After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 8-6.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
t1 | Power-on delay: delay from power up to logic level of REFBUF pin | 2 | ms | ||
t2 | RESET pulse width | 1 | us | ||
t3 | Delay from RESET disable to SEN active | ~ 200000 | clock cycles |