SBASAB5A March 2024 – December 2024 ADC3683-SP
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DC ACCURACY | ||||||
No missing codes | 18 | bits | ||||
PSRR | Power supply rejection ratio | FIN = 1MHz | 50 | dB | ||
DNL | Differential nonlinearity | FIN = 5MHz | -0.9 | ±0.7 | 1.8 | LSB |
INL | Integral nonlinearity | FIN = 5MHz | ±7 | ±23.5 | LSB | |
VOS | Input offset | ±130 | ±510 | LSB | ||
VOS_DRIFT | Offset drift | ±0.2 | LSB/ºC | |||
Error | Gain error and internal reference combined error | Both channels are powered up | -5.5 | ±2.1 | 5.5 | %FSR |
Fs = 10MSPS, both channels are powered up | -3 | ±0.5 | 3 | %FSR | ||
Gain error | Both channels are powered up | -5.2 | ±1.3 | 5.2 | %FSR | |
Fs = 10MSPS, both channels are powered up | -2.5 | ±0.2 | 2.5 | %FSR | ||
Gain drift | External 1.6V reference | 68 | ppm/ºC | |||
Internal reference | 242 | ppm/ºC | ||||
Transition noise | 5 | LSB | ||||
ADC ANALOG INPUT (AINP/M, BINP/M) | ||||||
FS | Input full scale | Differential | 3.2 | Vpp | ||
VCM | Input common-mode voltage | 0.95 | V | |||
RIN | Differential input resistance | FIN = 100kHz | 8 | kΩ | ||
CIN | Differential input capacitance | FIN = 100kHz | 7 | pF | ||
VOCM | Output common-mode voltage | 0.95 | V | |||
BW | Analog input bandwidth (-3dB) | 200 | MHz | |||
INTERAL VOLTAGE REFERENCE | ||||||
VREF | Internal reference voltage | 1.6 | V | |||
VREF output impedance | 8 | Ω | ||||
EXTERNAL VOLTAGE REFERENCE | ||||||
VREF | External voltage reference | 1.6 | V | |||
Input current | 0.35 | mA | ||||
Input impedance | 5.3 | kΩ | ||||
CLOCK INPUT (CLKP/M) | ||||||
Input clock frequency | 1 | 65 | MHz | |||
VID | Differential input voltage | 0.5 | 1 | Vpp | ||
VCM | Input common-mode voltage | 0.9 | V | |||
RIN | Single-ended input resistance to common mode | 5 | kΩ | |||
CIN | Single-ended input capacitance | 1.5 | pF | |||
Clock duty cycle | 40 | 50 | 60 | % | ||
DIGITAL INPUTS (RESET, PDN, SCLK, SEN, SDIO) | ||||||
VIH | High level input voltage | 1.5 | V | |||
VIL | Low level input voltage | 0.3 | V | |||
IIH | High level input current | 90 | 150 | uA | ||
IIL | Low level input current | -150 | -90 | uA | ||
CI | Input capacitance | 1.5 | pF | |||
DIGITAL OUTPUT (SDOUT) | ||||||
VOH | High level output voltage | ILOAD = -400uA | IOVDD – 0.1 | IOVDD | V | |
VOL | Low level output voltage | ILOAD = 400uA | 0.1 | V | ||
SLVDS INTERFACE | ||||||
LVDS lane rate | 1 | Gbps | ||||
VID | DCLKIN differential input voltage | 200 | 350 | mVpp | ||
VCM | DCLKIN input common-mode voltage | 1.1 | 1.2 | 1.3 | V | |
VOD | Differential output voltage | 0.585 | 700 | 0.785 | mVpp | |
VCM | Output common-mode voltage | 0.85 | 1.0 | 1.15 | V |