SBASAB5A March   2024  – December 2024 ADC3683-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter
          2. 7.3.1.2.2 AC Coupling
          3. 7.3.1.2.3 DC Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Differential Vs Single-ended Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference
      4. 7.3.4 Digital Data Path & Interface
        1. 7.3.4.1 Data Path Overview
        2. 7.3.4.2 Digital Interface
        3. 7.3.4.3 DCLKIN
        4. 7.3.4.4 Output Scrambler
        5. 7.3.4.5 Output Bit Mapper
          1. 7.3.4.5.1 2-Wire Mode
          2. 7.3.4.5.2 1-Wire Mode
          3. 7.3.4.5.3 1/2-Wire Mode
        6. 7.3.4.6 Output Data Format
        7. 7.3.4.7 Test Pattern
      5. 7.3.5 Digital Down Converter
        1. 7.3.5.1 Decimation Operation
        2. 7.3.5.2 Numerically Controlled Oscillator (NCO)
        3. 7.3.5.3 Decimation Filters
        4. 7.3.5.4 SYNC
        5. 7.3.5.5 Output Data Format with Decimation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Averaging Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Control
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
      3. 7.5.3 Device Configuration Steps
      4. 7.5.4 Register Map
        1. 7.5.4.1 Detailed Register Description
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Timing Requirements

Typical values are at TA = 25°C, MIN and MAX timing values are characterized over the full temperature range TMIN = –55°C to TMAX = 105°C and are NOT production tested, ADC sampling rate = 65MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8V, 1.6V external reference, and –1dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC TIMING SPECIFICATIONS
tAD Aperture delay 0.85 ns
tA Aperture jitter Square wave clock with fast edges 180 fs
tACQ Signal acquisition period, referenced to sampling clock falling edge FS = 10Msps -TS/2 Sampling clock period
FS = 25Msps -TS/2
FS = 65Msps -TS/4
tCONV Signal conversion period, referenced to sampling clock falling edge FS = 10Msps +TS × 1/5 Sampling clock period
FS = 25Msps +TS × 3/8
FS = 65Msps +TS × 5/8
Wake up time Time to valid data after coming out of power down External 1.6V reference, differential sampling clock 100 µs
tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps
tH,SYNC Hold time for SYNC input signal 600
ADC latency Signal input to data output SLVDS 2-wire 2 ADC clock cycles
SLVDS 1-wire 1
SLVDS 1/2-wire 1
Real decimation by 2 21   Output clock cycles
Complex decimation by 2   22  
Real or complex decimation by 4, 8, 16, 32   23  
INTERFACE TIMING: SERIAL LVDS INTERFACE
tPD Propagation delay: sampling clock falling edge to DCLK rising edge Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns.
tDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + tDCLK + tCDCLK 3 + tDCLK + tCDCLK 4 + tDCLK + tCDCLK ns
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns.
tDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + tCDCLK 3 + tCDCLK 4 + tCDCLK ns
tCD DCLK rising edge to output data delay Fout = 10MSPS, data rate = 90MBPS, 2-wire 0 0.1 0.3 ns
Fout = 65MSPS, data rate = 585MBPS, 2-wire 0 0.1 0.3
Fout = 10MSPS, data rate = 180MBPS, 1-wire 0.1 0.2 0.3
Fout = 55MSPS, data rate = 990MBPS, 1-wire -0.4 0.1 0.3
Fout = 5MSPS, data rate = 180MBPS, 1/2-wire 0 0.1 0.3
Fout = 25MSPS, data rate = 720MBPS, 1/2-wire 0 0.1 0.3
tDV Data valid Fout = 10MSPS, DA/B0,1 = 90MBPS, 2-wire 10.5 10.7 10.8 ns
Fout = 65MSPS, DA/B0,1 = 585MBPS, 2-wire 1.3 1.4 1.5
Fout = 10MSPS, DA/B0 = 180MBPS, 1-wire 4.7 4.8 4.9
Fout = 55MSPS, DA/B0 = 990MBPS, 1-wire 0.5 0.6 0.75
Fout = 5MSPS, DA0 = 180MBPS, 1/2-wire 4.7 4.8 4.9
Fout = 25MSPS, DA0 = 900MBPS, 1/2-wire 0.6 0.7 0.85
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - INPUT
fCLK(SCLK) Serial clock frequency 20 MHz
tSU(SEN) SEN to rising edge of SCLK 11 ns
tH(SEN) SEN from rising edge of SCLK 18 ns
tSU(SDIO) SDIO to rising edge of SCLK 18 ns
tH(SDIO) SDIO from rising edge of SCLK 11 ns
SERIAL PROGRAMMING INTERFACE (SDIO) - OUTPUT
t(OZD) SDIO HiZ to LoZ 20 ns
t(ODZ) SDIO LoZ to HiZ 18 ns
t(OD) Falling edge of SCLK to SDIO data valid 20 ns