SBASAB5 March 2024 ADC3683-SP
PRODMIX
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DC ACCURACY | ||||||
No missing codes | 18 | bits | ||||
PSRR | FIN = 1 MHz | 50 | dB | |||
ADC3683-SP: 65 MSPS | ||||||
DNL | Differential nonlinearity | FIN = 5 MHz | -0.9 | ± 0.7 | 1.7 | LSB |
INL | Integral nonlinearity | FIN = 5 MHz | ± 7 | ± 21.5 | LSB | |
VOS_ERR | Offset error | ± 130 | ± 510 | LSB | ||
VOS_DRIFT | Offset drift over temperature | ± 0.2 | LSB/ºC | |||
GAINERR | Gain error | External 1.6V Reference | ± 1.7 | %FSR | ||
GAINDRIFT | Gain drift over temperature | External 1.6V Reference | 68 | ppm/ºC | ||
GAINERR | Gain error | Internal Reference | -5 | 1.3 | +5 | %FSR |
Internal Reference, Fs= 10 MSPS | -2.5 | 0.2 | +2.5 | %FSR | ||
GAINDRIFT | Gain drift over temperature | Internal Reference | 242 | ppm/ºC | ||
Transition Noise | 5 | LSB | ||||
ADC ANALOG INPUT (AINP/M, BINP/M) | ||||||
FS | Input full scale | Differential | 3.2 | Vpp | ||
VCM | Input common model voltage | 0.95 | V | |||
RIN | Differential input resistance | FIN = 100 kHz | 8 | kΩ | ||
CIN | Differential input Capacitance | FIN = 100 kHz | 7 | pF | ||
VOCM | Output common mode voltage | 0.95 | V | |||
BW | Analog Input Bandwidth (-3dB) | 140 | MHz | |||
Internal Voltage Reference | ||||||
VREF | Internal reference voltage | 1.6 | V | |||
VREF Output Impedance | 8 | Ω | ||||
Reference Input Buffer (REFBUF) | ||||||
External reference voltage | 1.2 | V | ||||
External voltage reference (VREF) | ||||||
VREF | External voltage reference | 1.6 | V | |||
Input Current | 0.3 | mA | ||||
Input impedance | 5.3 | kΩ | ||||
Clock Input (CLKP/M) | ||||||
Input clock frequency | 1 | 65 | MHz | |||
VID | Differential input voltage | 1 | Vpp | |||
VCM | Input common mode voltage | 0.9 | V | |||
RIN | Single ended input resistance to common mode | 5 | kΩ | |||
CIN | Single ended input capacitance | 1.5 | pF | |||
Clock duty cycle | 40 | 50 | 60 | % | ||
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO) | ||||||
VIH | High level input voltage | 1.5 | V | |||
VIL | Low level input voltage | 0.3 | V | |||
IIH | High level input current | 90 | 150 | uA | ||
IIL | Low level input current | -150 | -90 | uA | ||
CI | Input capacitance | 1.5 | pF | |||
Digital Output (SDOUT) | ||||||
VOH | High level output voltage | ILOAD = -400 uA | IOVDD – 0.1 | IOVDD | V | |
VOL | Low level output voltage | ILOAD = 400 uA | 0.1 | V | ||
SLVDS Interface | ||||||
Output data rate | per differential SLVDS output pair | 1000 | Mbps | |||
VID | Differential input voltage | DCLKIN (1) | 350 | mVpp | ||
VCM | Input common mode voltage | 1.2 | V | |||
VOD | Differential output voltage | 700 | mVpp | |||
VCM | Output common mode voltage | 1.0 | V |