SBASAD1A December 2023 – May 2024 ADC3910D025 , ADC3910D065 , ADC3910D125 , ADC3910S025 , ADC3910S065 , ADC3910S125
PRODUCTION DATA
The ADC3910Dx and ADC3910Sx are a family ultra-low power 10-bit 125MSPS high-speed single and dual channel analog-to-digital converters. High-speed control loops benefit from the short latency of only 1 clock cycle. The ADC consumes only 92mW at 125Msps with a power consumption that scales with lower sampling rates.
The device uses DDR, HDDR, SDR or serial CMOS interface to output the data from +1.8V to +3.3V to accommodate various receiver requirements. The device implements analog monitoring function by event triggered interrupts per channel using a digital comparator with programmable high and low thresholds, hysteresis, and event counter. The device is a pin-to-pin compatible family of ADCs with 8 and 10-bit resolution and different speed grades. The device is available in a 32-pin VQFN package, and supports industrial temperature range from -40 to +105°C.
PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) |
---|---|---|
ADC3910D025, 'D065, 'D125 ADC3910S025,'S065, 'S125 | VQFN (32) | 4mm × 4mm |
PART NUMBER (c= #CH; sss= MSPS) | RESOLUTION | SAMPLING RATE MSPS |
---|---|---|
ADC3910csss | 10-Bit | 25, 65, 125 |
ADC3908csss | 08-Bit | 25, 65, 125 |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
INPUT or REFERENCE | |||
INAP | 10 | I | Positive analog input, channel A |
INAM | 11 | I | Negative analog input, channel A |
INBP/NC | 14 | I | Positive analog input, channel B (NC on single channel device) |
INBM/NC | 15 | I | Negative analog input, channel B (NC on single channel device) |
VREF | 17 | I | 1.2V external voltage reference input. A 10μF and a 0.1μF ceramic bypass capacitor connected between VREF and GND pins and placed as close to the pins as possible is recommended when using external reference. Otherwise, connect to GND when using internal reference. |
VCM | 7 | O | Common-mode voltage output to provide DC bias for the analog inputs, 1.25V |
CLOCK | |||
CLK | 8 | I | Sampling clock input for the ADC |
CONFIGURATION | |||
RESET | 9 | I | Hardware reset. Active high. This pin has an internal 60kΩ pull-down resistor. |
SEN | 16 | I | Serial interface enable, Active low, internal 40kΩ pull-down resistor. |
SCLK | 18 | I | Serial interface clock input, internal 40kΩ pull-down resistor. |
SDIO | 19 | I/O | Serial interface data input and output, internal 40kΩ pull-down resistor. |
ALERT | 20 | O | Digital window comparator status pin or over range alert. |
DIGITAL INTERFACE | |||
D0 | 4 | O | CMOS digital lane output data. |
D1 | 3 | O | |
D2 | 2 | O | |
D3 | 1 | O | |
D4 | 32 | O | |
D5 | 31 | O | |
D6 | 26 | O | |
D7 | 25 | O | |
D8 | 24 | O | |
D9 | 23 | O | |
D10 | 22 | O | |
D11 | 21 | O | |
DCLK | 30 | O | CMOS output for data bit clock. |
DCLK/FCLK | 29 | O | Default is Inverse data bit clock for CMOS output data. Frame clock can be selected via SPI write |
OEN/PD | 6 | I | Output data enable. This pin is active low with default 60kΩ pull-down. Can be configured as power down pin through SPI. |
POWER SUPPLY | |||
AVDD | 12, 13 | I | Analog 1.8V power supply |
GND | PowerPAD™ | I | Analog Ground, 0V |
IOVDD | 27 | I | 1.8V to 3.3V power supply for digital interface |
DGND | 28 | I | Ground, 0V for digital interface |
OTHER | |||
NC | 17 | N/A | No connection. Connect to ground |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT |
---|---|---|---|---|
Supply voltage range 1.8 V, AVDD | –0.3 | 2.1 | V | |
Supply voltage range 1.8 V to 3.3 V, IOVDD | –0.3 | 3.6 | ||
Supply voltage range, GND, DGND | –0.3 | 0.3 | ||
Voltage applied to input pins | INAP/M, INBP/M, CLK, DCLKIN | –0.3 | 2.1 | |
VREF | –0.3 | 2.1 | ||
RESET, SCLK, SEN, SDIO, OEN | –0.3 | 2.1 | ||
Junction temperature, TJ | 110 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | 1000 | V |
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) | 500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Supply voltage range | Supply voltage range 1.8v | AVDD(1) | 1.7 | 1.8 | 1.9 | V |
Supply voltage range | IOVDD(1) | 1.7 | 1.8 | 1.9 | V | |
Supply voltage range | Supply voltage range 3.3v | IOVDD(1) | 3.2 | 3.3 | 3.4 | V |
TA | Operating free-air temperature | –40 | 105 | °C | ||
TJ | Operating junction temperature | 105(2) | °C |
THERMAL METRIC(1) | ADC39xx | UNIT | |
---|---|---|---|
RSM (QFN) | |||
32 Pins | |||
RΘJA | Junction-to-ambient thermal resistance | 38.1 | °C/W |
RΘJC(top) | Junction-to-case (top) thermal resistance | 37.2 | °C/W |
RΘJB | Junction-to-board thermal resistance | 17.9 | °C/W |
ΨJT | Junction-to-top characterization parameter | 1 | °C/W |
ΨJB | Junction-to-board characterization parameter | 17.9 | °C/W |
RΘJC(bot) | Junction-to-case (bottom) thermal resistance | 7.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ADC3910D025 | ||||||
IAVDD | Analog supply current | FS = 25 MSPS, dual channel | 29 | 31 | mA | |
IIOVDD | Digital supply current | 4 | 9 | mA | ||
PDIS | Power dissipation | 59 | mW | |||
ADC3910S025 | ||||||
IAVDD | Analog supply current | FS = 25 MSPS, single channel | 19 | 22 | mA | |
IIOVDD | Digital supply current | 4 | 8 | mA | ||
PDIS | Power dissipation | 41 | mW | |||
ADC3910D065 | ||||||
IAVDD | Analog supply current | FS = 65 MSPS, dual channel | 33 | 36 | mA | |
IIOVDD | Digital supply current | 9 | 18 | mA | ||
PDIS | Power dissipation | 76 | mW | |||
ADC3910S065 | ||||||
IAVDD | Analog supply current | FS = 65 MSPS, single channel | 22 | 24 | mA | |
IIOVDD | Digital supply current | 10 | 19 | mA | ||
PDIS | Power dissipation | 58 | mW | |||
ADC3910D125 | ||||||
IAVDD | Analog supply current | FS = 125 MSPS, dual channel | 39 | 44 | mA | |
IIOVDD | Digital supply current | 15 | 18.5 | mA | ||
PDIS | Power dissipation | 97 | mW | |||
ADC3910S125 | ||||||
IAVDD | Analog supply current | FS = 125 MSPS, single channel | 25 | 28 | mA | |
IIOVDD | Digital supply current | 19 | 32 | mA | ||
PDIS | Power dissipation | 80 | mW | |||
Power down | ||||||
PDIS | Power consumption in global power down mode | 4 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DC ACCURACY (25 MSPS) | ||||||
No missing codes | No missing codes | 10 | bits | |||
DNL | Differential nonlinearity | -0.95 | ±0.4 | 2.1 | LSB | |
INL | Integral nonlinearity | -2 | ±0.5 | 2.1 | LSB | |
VOS_ERR | Offset error | -2.75 | ±1 | 2.75 | LSB | |
VOS_DRIFT | Offset drift over temperature | 0.001 | LSB/ºC | |||
GAINERR | Gain error | External Reference | -2.25 | ±0.2 | 2.25 | %FSR |
Internal Reference | ±0.8 | %FSR | ||||
GAINDRIFT | Gain drift over temperature | External Reference | -35 | ppm/ºC | ||
Internal Reference | -102 | ppm/ºC | ||||
DC ACCURACY (65 MSPS) | ||||||
No missing codes | No missing codes | 10 | bits | |||
DNL | Differential nonlinearity | -0.95 | ±0.4 | 2.1 | LSB | |
INL | Integral nonlinearity | -2 | ±0.5 | 2.1 | LSB | |
VOS_ERR | Offset error | -2.75 | ±1 | 2.75 | LSB | |
VOS_DRIFT | Offset drift over temperature | 0.001 | LSB/ºC | |||
GAINERR | Gain error | External Reference | -2.25 | ±0.2 | 2.25 | %FSR |
Internal Reference | ±0.8 | %FSR | ||||
GAINDRIFT | Gain drift over temperature | External Reference | -35 | ppm/ºC | ||
Internal Reference | -102 | ppm/ºC | ||||
DC ACCURACY (125 MSPS) | ||||||
No missing codes | No missing codes | 10 | bits | |||
DNL | Differential nonlinearity | -0.95 | ±0.4 | 2.1 | LSB | |
INL | Integral nonlinearity | -2 | ±0.5 | 2.1 | LSB | |
VOS_ERR | Offset error | -2.75 | ±1 | 2.75 | LSB | |
VOS_DRIFT | Offset drift over temperature | 0.001 | LSB/ºC | |||
GAINERR | Gain error | External Reference | -2.25 | ±0.3 | 2.25 | %FSR |
Internal Reference | ±0.8 | %FSR | ||||
GAINDRIFT | Gain drift over temperature | External Reference | -35 | ppm/ºC | ||
Internal Reference | -102 | ppm/ºC | ||||
ADC ANALOG INPUT (INAP/M, INBP/M) | ||||||
FS | Input full scale | Differential | 1.9 | Vpp | ||
Single-ended | 0.95 | Vpp | ||||
CIN | Differential input Capacitance | FIN = 100 kHz | 7 | pF | ||
VCM | Input common mode voltage | VOCM - 50mV | 1.275 | VOCM + 50mV | V | |
VOCM | Output common mode voltage | 1.25 | V | |||
BW | Analog Input Bandwidth (-3dB) | 150 | MHz | |||
EXTERNAL VOLTAGE REFERENCE (VREF) | ||||||
VREF | External voltage reference | 1.2 | V | |||
Input Current | 0.1 | mA | ||||
Input impedance | 12 | kΩ | ||||
CLOCK INPUT | ||||||
Input clock frequency | 5 | 125 | MHz | |||
VIH | High level input voltage | AVDD - 0.3 | 1.8 | V | ||
VIL | Low level input voltage | 0 | AVSS + 0.3 | V | ||
CIN | Input capacitance | 0.5 | pF | |||
Clock duty cycle | 45 | 50 | 55 | % | ||
DIGITAL INPUTS (DCLKIN, RESET, OEN, SCLK, SEN, SDIO) | ||||||
VIH | High level input voltage | DCLKIN | AVDD - 0.1 | AVDD | V | |
VIL | Low level input voltage | 0.1 | V | |||
VIH | High level input voltage | RESET, OEN, SCLK, SEN, SDIO | 1.4 | V | ||
VIL | Low level input voltage | 0.4 | V | |||
IIH | High level input current | 90 | 150 | uA | ||
IIL | Low level input current | -150 | -90 | uA | ||
CI | Input capacitance | 1.5 | pF | |||
DIGITAL OUTPUT (SDOUT) | ||||||
VOH | High level output voltage | ILOAD = -400 uA | AVDD - 0.1 | AVDD | V | |
VOL | Low level output voltage | ILOAD = 400 uA | 0.1 | V | ||
DIGITAL CMOS OUTPUTS (D0:D11) | ||||||
Output data rate | per CMOS output pin | 250 | MHz | |||
VOH | High level output voltage | ILOAD = -400 uA | IOVDD - 0.1 | IOVDD | V | |
VOL | Low level output voltage | ILOAD = 400 uA | 0.1 | V | ||
VOH | High level output voltage | ILOAD = -400 uA, ALERT/GPO | IOVDD - 0.1 | IOVDD | V | |
VOL | Low level output voltage | 0.1 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
NSD | Noise Spectral Density | fIN = 10 MHz, AIN = -20 dBFS | -132 | dBFS/Hz | ||
SNR | Signal to noise ratio, excluding DC, HD2 to HD5 | fIN = 1.1 MHz | 61.1 | dBFS | ||
fIN = 5 MHz | 57 | 60.7 | ||||
fIN = 10 MHz | 61.1 | |||||
fIN = 20 MHz | 61.0 | |||||
SINAD | Signal to noise and distortion ratio, excluding DC offset | fIN = 1.1 MHz | 59.1 | dBFS | ||
fIN = 5 MHz | 59.9 | |||||
fIN = 10 MHz | 59.7 | |||||
fIN = 20 MHz | 59.8 | |||||
ENOB | Effective number of bits, excluding DC offset | fIN = 1.1 MHz | 9.9 | Bit | ||
fIN = 5 MHz | 9.9 | |||||
fIN = 10 MHz | 9.8 | |||||
fIN = 20 MHz | 9.8 | |||||
THD | Total Harmonic Distortion (First five harmonics) | fIN = 1.1 MHz | -62 | dBc | ||
fIN = 5 MHz | -65 | |||||
fIN = 10 MHz | -65 | |||||
fIN = 20 MHz | -65 | |||||
SFDR | Spur free dynamic range including second and third harmonic | fIN = 1.1 MHz | 63 | dBFS | ||
fIN = 5 MHz | 57 | 66 | ||||
fIN = 10 MHz | 65 | |||||
fIN = 20 MHz | 65 | |||||
SPUR | Spur free dynamic range (excluding DC, HD2, HD3) | fIN = 1.1 MHz | 83 | dBFS | ||
fIN = 5 MHz | 58 | 85 | ||||
fIN = 10 MHz | 85 | |||||
fIN = 20 MHz | 82 | |||||
IMD3 | Two tone inter-modulation distortion | fIN = 10/12 MHz, AIN = -7 dBFS/tone | -98 | dBc | ||
XTALK | Channel-to-channel crosstalk | Aggressor = 1.1 MHz | 107 | dBFS | ||
Aggressor = 10 MHz | 97 | |||||
Aggressor = 20 MHz | 93 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
NSD | Noise Spectral Density | fIN = 10 MHz, AIN = -20 dBFS | -135.9 | dBFS/Hz | ||
SNR | Signal to noise ratio, excluding DC, HD2 to HD5 | fIN = 1.1 MHz | 61.0 | dBFS | ||
fIN = 5 MHz | 57 | 61.1 | ||||
fIN = 10 MHz | 61.1 | |||||
fIN = 20 MHz | 61.1 | |||||
fIN = 40 MHz | 61.0 | |||||
fIN = 70 MHz | 60.7 | |||||
SINAD | Signal to noise and distortion ratio, excluding DC offset | fIN = 1.1 MHz | 59.2 | dBFS | ||
fIN = 5 MHz | 59.7 | |||||
fIN = 10 MHz | 59.8 | |||||
fIN = 20 MHz | 60.0 | |||||
fIN = 40 MHz | 59.5 | |||||
fIN = 70 MHz | 58.5 | |||||
ENOB | Effective number of bits, excluding DC offset | fIN = 1.1 MHz | 9.8 | Bit | ||
fIN = 5 MHz | 9.9 | |||||
fIN = 10 MHz | 9.9 | |||||
fIN = 20 MHz | 9.8 | |||||
fIN = 40 MHz | 9.8 | |||||
fIN = 70 MHz | 9.8 | |||||
THD | Total Harmonic Distortion (First five harmonics) | fIN = 1.1 MHz | -62 | dBc | ||
fIN = 5 MHz | -64 | |||||
fIN = 10 MHz | -65 | |||||
fIN = 20 MHz | -66 | |||||
fIN = 40 MHz | -64 | |||||
fIN = 70 MHz | -62 | |||||
SFDR | Spur free dynamic range including second and third harmonic | fIN = 1.1 MHz | 63 | dBFS | ||
fIN = 5 MHz | 57 | 65 | ||||
fIN = 10 MHz | 65 | |||||
fIN = 20 MHz | 66 | |||||
fIN = 40 MHz | 64 | |||||
fIN = 70 MHz | 62 | |||||
SPUR | Spur free dynamic range (excluding DC, HD2, HD3) | fIN = 1.1 MHz | 85 | dBFS | ||
fIN = 5 MHz | 58 | 85 | ||||
fIN = 10 MHz | 85 | |||||
fIN = 20 MHz | 82 | |||||
fIN = 40 MHz | 77 | |||||
fIN = 70 MHz | 71 | |||||
IMD3 | Two tone inter-modulation distortion | fIN = 10/12 MHz, AIN = -7 dBFS/tone | -94 | dBc | ||
XTALK | Channel-to-channel crosstalk | Aggressor = 1.1 MHz | 105 | dBFS | ||
Aggressor = 10 MHz | 102 | |||||
Aggressor = 20 MHz | 97 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
NSD | Noise Spectral Density | fIN = 10 MHz, AIN = -20 dBFS | -138.8 | dBFS/Hz | ||
SNR | Signal to noise ratio, excluding DC, HD2 to HD5 | fIN = 1.1 MHz | 60.8 | dBFS | ||
fIN = 5 MHz | 57 | 60.6 | ||||
fIN = 10 MHz | 60.6 | |||||
fIN = 20 MHz | 60.6 | |||||
fIN = 40 MHz | 60.6 | |||||
fIN = 70 MHz | 60.4 | |||||
SINAD | Signal to noise and distortion ratio, excluding DC offset | fIN = 1.1 MHz | 58.5 | dBFS | ||
fIN = 5 MHz | 58.9 | |||||
fIN = 10 MHz | 59.1 | |||||
fIN = 20 MHz | 59.1 | |||||
fIN = 40 MHz | 59.6 | |||||
fIN = 70 MHz | 57.7 | |||||
ENOB | Effective number of bits, excluding DC offset | fIN = 1.1 MHz | 9.8 | Bit | ||
fIN = 5 MHz | 9.8 | |||||
fIN = 10 MHz | 9.8 | |||||
fIN = 20 MHz | 9.8 | |||||
fIN = 40 MHz | 9.8 | |||||
fIN = 70 MHz | 9.7 | |||||
THD | Total Harmonic Distortion (First five harmonics) | fIN = 1.1 MHz | -61 | dBc | ||
fIN = 5 MHz | -63 | |||||
fIN = 10 MHz | -63 | |||||
fIN = 20 MHz | -64 | |||||
fIN = 40 MHz | -65 | |||||
fIN = 70 MHz | -60 | |||||
SFDR | Spur free dynamic range including second and third harmonic | fIN = 1.1 MHz | 62 | dBFS | ||
fIN = 5 MHz | 57 | 64 | ||||
fIN = 10 MHz | 64 | |||||
fIN = 20 MHz | 65 | |||||
fIN = 40 MHz | 67 | |||||
fIN = 70 MHz | 61 | |||||
SPUR | Spur free dynamic range (excluding DC, HD2, HD3) | fIN = 1.1 MHz | 84 | dBFS | ||
fIN = 5 MHz | 58 | 82 | ||||
fIN = 10 MHz | 84 | |||||
fIN = 20 MHz | 82 | |||||
fIN = 40 MHz | 78 | |||||
fIN = 70 MHz | 75 | |||||
IMD3 | Two tone inter-modulation distortion | fIN = 10/12 MHz, AIN = -7 dBFS/tone | -84 | dBc | ||
fIN = 90/92 MHz, AIN = -7 dBFS/tone | -97 | |||||
XTALK | Channel-to-channel crosstalk | Aggressor = 1.1 MHz | 102 | dBFS | ||
Aggressor = 10 MHz | 90 | |||||
Aggressor = 20 MHz | 98 |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
ADC TIMING SPECIFICATIONS | ||||||
tAD | Aperture Delay | 0.5 | ns | |||
tA | Aperture Jitter | square wave clock with fast edges | 500 | fs | ||
tACQ | Signal acquisition period, referenced to sampling clock falling edge | -TS/5 | Sampling Clock Period | |||
tCONV | Signal conversion period, referenced to sampling clock falling edge | Fs = 25 MSPS | 5.5 | ns | ||
Fs = 65 MSPS | 5.5 | ns | ||||
Fs = 125 MSPS | 5.5 | ns | ||||
Wake up time | Time to valid data after coming out of power down. Internal reference. | 30 | us | |||
Time to valid data after coming out of power down. External 1.2V reference. | 19 | us | ||||
ADC Latency | Signal input to data output | Low Latency Mode(1) | 1 | ADC clock cycles | ||
Digital features enabled (includes Serial CMOS interface modes) | 5 | |||||
Add. Latency | Real Decimation | 2 | 25 | |||
4 | 60 | |||||
8 | 130 | |||||
16 | 270 | |||||
INTERFACE TIMING - DDR CMOS | ||||||
tPD | Propagation delay: sampling clock falling edge to DCLK rising edge | TS/4 + 3 | ns | |||
tDE | DCLK edge to previous data transition | Fs = 25 MSPS | -10 | -9 | ||
Fs = 65 MSPS | -3.8 | -3.4 | ||||
Fs = 125 MSPS | -2 | -1.8 | ||||
tDL | DCLK edge to next data transition | Fs = 25 MSPS | 9 | 10 | ||
Fs = 65 MSPS | 3.4 | 3.8 | ||||
Fs = 125 MSPS | 1.8 | 2 | ||||
INTERFACE TIMING - SDR CMOS | ||||||
tPD | Propagation delay: sampling clock falling edge to DCLK rising edge | TS/4 + 3 | ns | |||
tDE | DCLK edge to previous data transition | Fs = 25 MSPS | -20 | -18 | ||
Fs = 65 MSPS | -7.6 | -6.9 | ||||
Fs = 125 MSPS | -4 | -3.6 | ||||
tDV | DCLK edge to next data transition | Fs = 25 MSPS | 18 | 20 | ||
Fs = 65 MSPS | 6.9 | 7.7 | ||||
Fs = 125 MSPS | 3.6 | 4 | ||||
tPD | Propagation delay: sampling clock falling edge to output data delay | Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge |
TS/4 + 3 | ns | ||
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge |
TS/4 + 3 | |||||
tCD | DCLK rising edge to output data delay 4 Lane serial CMOS |
Fout = 10 MSPS | -7.25 | -6.25 | -5.25 | ns |
Fout = 20 MSPS | -4.125 | -3.125 | -2.125 | |||
Fout = 30 MSPS | -3.08 | -2.08 | -1.08 | |||
DCLK rising edge to output data delay 2 Lane serial CMOS |
Fout = 5 MSPS | -7.25 | -6.25 | -5.25 | ||
Fout = 10 MSPS | -4.125 | -3.125 | -2.125 | |||
Fout = 15 MSPS | -3.08 | -2.08 | -1.08 | |||
tDV | Data valid, 4 Lane serial CMOS | Fout = 10 MSPS | -7.25 | -6.25 | -5.25 | ns |
Fout = 20 MSPS | -4.125 | -3.125 | -2.125 | |||
Fout = 30 MSPS | -3.08 | -2.08 | -1.08 | |||
Data valid, 2 Lane serial CMOS | Fout = 5 MSPS | -7.25 | -6.25 | -5.25 | ||
Fout = 10 MSPS | -4.125 | -3.125 | -2.125 | |||
Fout = 15 MSPS | -3.08 | -2.08 | -1.08 | |||
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input | ||||||
fCLK,SCLK | Serial clock frequency | 20 | MHz | |||
tS,SEN | SEN falling edge to SCLK rising edge | 10 | ns | |||
tH,SEN | SCLK rising edge to SEN rising edge | 10 | ||||
tS,SDIO | SDIO setup time from rising edge of SCLK | 17 | ||||
tH,SDIO | SDIO hold time from rising edge of SCLK | 9 | ||||
SERIAL PROGRAMMING INTERFACE (SDIO) - Output | ||||||
tOZD | Delay from falling edge of 8th SCLK cycle during read operation for SDIO transition from tri-state to valid data | 3.9 | 10.8 | ns | ||
tODZ | Delay from SEN rising edge for SDIO transition from valid data to tri-state | 3.4 | 14 | |||
tOD | Delay from falling edge of 8th SCLK cycle during read operation to SDIO valid | 3.9 | 10.8 |
Typical values at TA = 25°C, ADC sampling rate = 25MSPS, AIN = –1dBFS, differential input, AVDD = IOVDD = 1.8V, internal 1.2V voltage reference, unless otherwise noted.
SNR = 61.2dBFS, SFDR = 64dBc, Non HD23 = 84dBFS |
SNR = 61dBFS, SFDR = 65dBc, Non HD23 = 87dBFS |
AIN = -7dBFS/tone, IMD3 = -98dBc |
FIN = 1MHz |
FIN = 1MHz |
FIN = 5MHz |
Pulse Input = 1MHz |
FIN = 1MHz, 16 bit resolution, DDR, 8 Output Lanes |
FIN = 5MHz |
SNR = 59dBFS, SFDR = 63dBc, Non HD23 = 85dBFS |
SNR = 61.2dBFS, SFDR = 63dBc, Non HD23 = 83dBFS |
FIN = 1MHz |
FIN = 1MHz |
FIN = 5MHz |
FIN = 5MHz, DDC Bypass |
FIN = 5MHz, DDR Interface Mode |
Typical values at TA = 25°C, ADC sampling rate = 65 MSPS, AIN = –1dBFS, differential input, AVDD = IOVDD = 1.8V, internal 1.2V voltage reference, unless otherwise noted.
SNR = 61dBFS, SFDR = 64dBc, Non-HD23 = 88dBFS |
SNR = 61dBFS, SFDR = 66dBc, Non-HD23 = 85dBFS |
SNR = 60.9dBFS, SFDR = 64dBc, Non-HD23 = 79dBFS |
FIN = 5MHz |
FIN = 5MHz |
FIN = 5MHz |
FIN = 5MHz, DDC Bypass |
FIN = 5MHz |
SNR = 58.3dBFS, SFDR = 57dBc, Non-HD23 = 76dBFS |
SNR = 61.3dBFS, SFDR = 64dBc, Non-HD23 = 84dBFS |
AIN = -7dBFS/tone, IMD3 = -94dBc |
FIN = 5MHz |
FIN = 5MHz |
FIN = 5MHz |
Pulse Input = 1MHz |
FIN = 1MHz, 16 bit resolution, DDR, 8 Output Lanes |
FIN = 5MHz |
Typical values at TA = 25°C, ADC sampling rate = 125MSPS, AIN = –1dBFS, differential input, AVDD = IOVDD = 1.8V, internal 1.2V voltage reference, unless otherwise noted.
SNR = 60.6dBFS, SFDR = 63.5dBc, Non-HD23 = 83.5dBFS |
SNR = 60.5dBFS, SFDR = 63dBc, Non-HD23 = 86dBFS |
SNR = 58.9dBFS, SFDR = 61.2dBc, Non-HD23 = 72dBFS |
SNR = 59.1dBFS, SFDR = 66dBc, Non-HD23 = 71dBFS |
AIN = -7dBFS/tone, IMD3 = -97dBc |
FIN = 5MHz |
FIN = 5MHz, AIN = -1dBFS on aggressor channel |
FIN = 10MHz |
FIN = 5MHz |
Pulse Input = 1MHz |
FIN = 1MHz, 16 bit resolution, DDR, 8 Output Lanes |
FIN = 5MHz |
SNR = 60.9dBFS, SFDR = 64dBc, Non-HD23 = 84dBFS |
SNR = 60.2dBFS, SFDR = 67dBc, Non-HD23 = 78dBFS |
SNR = 60.9dBFS, SFDR = 63dBc, Non-HD23 = 83dBFS |
AIN = -7dBFS/tone, IMD3 = -84dBc |
FIN = 10MHz |
FIN = 5MHz |
FIN = 5MHz |
FIN = 5MHz, DDC Bypass |
FIN = 5MHz |