SBASAD1A December   2023  – May 2024 ADC3910D025 , ADC3910D065 , ADC3910D125 , ADC3910S025 , ADC3910S065 , ADC3910S125

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 5.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 5.10 Timing Requirements
    11. 5.11 Output Interface Timing Diagram
    12. 5.12 Typical Characteristics - 25MSPS
    13. 5.13 Typical Characteristics - 65MSPS
    14. 5.14 Typical Characteristics - 125MSPS
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ADC Features
        1. 6.3.1.1 Low Latency Mode
        2. 6.3.1.2 Full Digital Feature Mode
        3. 6.3.1.3 Interleaving Mode
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Single Ended Input
        2. 6.3.2.2 Differential Input
        3. 6.3.2.3 Analog Input Bandwidth
      3. 6.3.3 Sampling Clock Input
      4. 6.3.4 Voltage Reference
      5. 6.3.5 Over-range (OVR)
      6. 6.3.6 Digital Features
        1. 6.3.6.1 Digital Down Converter
          1. 6.3.6.1.1 Digital Down Converter Data Select
          2. 6.3.6.1.2 Decimation Filter
          3. 6.3.6.1.3 DDC Over-range
          4. 6.3.6.1.4 Output Formatting with Decimation
        2. 6.3.6.2 Digital Comparator
          1. 6.3.6.2.1 Comparator Data Select
          2. 6.3.6.2.2 Comparator High and Low Threshold
          3. 6.3.6.2.3 Comparator Configuration Compare Mode
          4. 6.3.6.2.4 Comparator Event Configuration
        3. 6.3.6.3 Statistics Engine
          1. 6.3.6.3.1 Statistics Engine Data Select
          2. 6.3.6.3.2 Window Configuration
        4. 6.3.6.4 Digital Alerts
      7. 6.3.7 Digital Interface
        1. 6.3.7.1 Parallel CMOS Output
        2. 6.3.7.2 Serialized CMOS Output
      8. 6.3.8 Test Patterns
        1. 6.3.8.1 Bypass Test Pattern
        2. 6.3.8.2 Digital Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Power Down Options
    5. 6.5 Programming
      1. 6.5.1 Configuration using the SPI interface
        1. 6.5.1.1 Register Write
        2. 6.5.1.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Register Descriptions
      2. 6.6.2 Statistics Engine Register Map
      3. 6.6.3 Alerts Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Sampling Clock
        3. 7.2.2.3 Voltage Reference
      3. 7.2.3 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Register Initialization During Operation
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10 Timing Requirements

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, Internal 1.2 V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC TIMING SPECIFICATIONS
tAD Aperture Delay 0.5 ns
tA Aperture Jitter square wave clock with fast edges 500 fs
tACQ Signal acquisition period, referenced to sampling clock falling edge -TS/5 Sampling Clock Period
tCONV Signal conversion period, referenced to sampling clock falling edge Fs = 25 MSPS 5.5 ns
Fs = 65 MSPS 5.5 ns
Fs = 125 MSPS 5.5 ns
Wake up time Time to valid data after coming out of power down. Internal reference. 30 us
Time to valid data after coming out of power down. External  1.2V reference. 19 us
ADC Latency Signal input to data output Low Latency Mode(1) 1 ADC clock cycles
Digital features enabled (includes Serial CMOS interface modes) 5
Add. Latency Real Decimation 2 25
4 60
8 130
16 270
INTERFACE TIMING - DDR CMOS
tPD Propagation delay: sampling clock falling edge to DCLK rising edge TS/4 + 3 ns
tDE DCLK edge to previous data transition Fs = 25 MSPS -10 -9
Fs = 65 MSPS -3.8 -3.4
Fs = 125 MSPS -2 -1.8
tDL DCLK edge to next data transition Fs = 25 MSPS 9 10
Fs = 65 MSPS 3.4 3.8
Fs = 125 MSPS 1.8 2
INTERFACE TIMING - SDR CMOS
tPD Propagation delay: sampling clock falling edge to DCLK rising edge TS/4 + 3 ns
tDE DCLK edge to previous data transition Fs = 25 MSPS -20 -18
Fs = 65 MSPS -7.6 -6.9
Fs = 125 MSPS -4 -3.6
tDV DCLK edge to next data transition Fs = 25 MSPS 18 20
Fs = 65 MSPS 6.9 7.7
Fs = 125 MSPS 3.6 4
tPD Propagation delay: sampling clock falling edge to output data delay Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 TS/4 + 3 ns
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 TS/4 + 3
tCD DCLK rising edge to output data delay
4 Lane serial CMOS		 Fout = 10 MSPS -7.25 -6.25 -5.25 ns
Fout = 20 MSPS -4.125 -3.125 -2.125
Fout = 30 MSPS -3.08 -2.08 -1.08
DCLK rising edge to output data delay
2 Lane serial CMOS		 Fout = 5 MSPS -7.25 -6.25 -5.25
Fout = 10 MSPS -4.125 -3.125 -2.125
Fout = 15 MSPS -3.08 -2.08 -1.08
tDV Data valid, 4 Lane serial CMOS Fout = 10 MSPS -7.25 -6.25 -5.25 ns
Fout = 20 MSPS -4.125 -3.125 -2.125
Fout = 30 MSPS -3.08 -2.08 -1.08
Data valid, 2 Lane serial CMOS Fout = 5 MSPS -7.25 -6.25 -5.25
Fout = 10 MSPS -4.125 -3.125 -2.125
Fout = 15 MSPS -3.08 -2.08 -1.08
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK,SCLK Serial clock frequency 20 MHz
tS,SEN SEN falling edge to SCLK rising edge 10 ns
tH,SEN SCLK rising edge to SEN rising edge 10
tS,SDIO SDIO setup time from rising edge of SCLK 17
tH,SDIO SDIO hold time from rising edge of SCLK 9
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
tOZD Delay from falling edge of 8th SCLK cycle during read operation for SDIO transition from tri-state to valid data 3.9 10.8 ns
tODZ Delay from SEN rising edge for SDIO transition from valid data to tri-state 3.4 14
tOD Delay from falling edge of 8th SCLK cycle during read operation to SDIO valid 3.9 10.8
(1) In low latency mode the default interface is DDR for dual channel devices and SDR for single channel devices. Other interface configurations such as serial CMOS will add additional latency.