SBAS661C February   2015  – May 2021 ADS1262 , ADS1263

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Offset Temperature Drift Measurement
    2. 8.2 Gain Temperature Drift Measurement
    3. 8.3 Common-Mode Rejection Ratio Measurement
    4. 8.4 Power-Supply Rejection Ratio Measurement
    5. 8.5 Crosstalk Measurement (ADS1263)
    6. 8.6 Reference-Voltage Temperature-Drift Measurement
    7. 8.7 Reference-Voltage Thermal-Hysteresis Measurement
    8. 8.8 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multifunction Analog Inputs
      2. 9.3.2  Analog Input Description
        1. 9.3.2.1 ESD Diode
        2. 9.3.2.2 Input Multiplexer
      3. 9.3.3  Sensor Bias
      4. 9.3.4  Temperature Sensor
      5. 9.3.5  Power-Supply Monitor
      6. 9.3.6  PGA
      7. 9.3.7  PGA Voltage Overrange Monitors
        1. 9.3.7.1 PGA Differential Output Monitor
        2. 9.3.7.2 PGA Absolute Output-Voltage Monitor
      8. 9.3.8  ADC Reference Voltage
        1. 9.3.8.1 Internal Reference
        2. 9.3.8.2 External Reference
        3. 9.3.8.3 Power-Supply Reference
        4. 9.3.8.4 Low-Reference Monitor
      9. 9.3.9  ADC1 Modulator
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Sinc Filter Mode
          1. 9.3.10.1.1 Sinc Filter Frequency Response
        2. 9.3.10.2 FIR Filter
        3. 9.3.10.3 50-Hz and 60-Hz Line Cycle Rejection
      11. 9.3.11 Sensor-Excitation Current Sources (IDAC1 and IDAC2)
      12. 9.3.12 Level-Shift Voltage
      13. 9.3.13 General-Purpose Input/Output (GPIO)
      14. 9.3.14 Test DAC (TDAC)
      15. 9.3.15 ADC2 (ADS1263)
        1. 9.3.15.1 ADC2 Inputs
        2. 9.3.15.2 ADC2 PGA
        3. 9.3.15.3 ADC2 Reference
        4. 9.3.15.4 ADC2 Modulator
        5. 9.3.15.5 ADC2 Digital Filter
    4. 9.4 Device Functional Modes
      1. 9.4.1  Conversion Control
        1. 9.4.1.1 Continuous Conversion Mode
        2. 9.4.1.2 Pulse Conversion Mode
        3. 9.4.1.3 ADC2 Conversion Control (ADS1263)
      2. 9.4.2  Conversion Latency
      3. 9.4.3  Programmable Time Delay
      4. 9.4.4  Serial Interface
        1. 9.4.4.1 Chip Select (CS)
        2. 9.4.4.2 Serial Clock (SCLK)
        3. 9.4.4.3 Data Input (DIN)
        4. 9.4.4.4 Data Output/Data Ready (DOUT/DRDY)
        5. 9.4.4.5 Serial Interface Autoreset
      5. 9.4.5  Data Ready Pin (DRDY)
      6. 9.4.6  Conversion Data Software Polling
      7. 9.4.7  Read Conversion Data
        1. 9.4.7.1 Read Data Direct (ADC1 Only)
        2. 9.4.7.2 Read Data by Command
        3. 9.4.7.3 Data-Byte Sequence
          1. 9.4.7.3.1 Status Byte
          2. 9.4.7.3.2 Data Byte Format
          3. 9.4.7.3.3 Checksum Byte (CRC/CHK)
            1. 9.4.7.3.3.1 Checksum Mode (CRC[1:0] = 01h)
          4. 9.4.7.3.4 CRC Mode (CRC[1:0] = 10h)
      8. 9.4.8  ADC Clock Modes
        1. 9.4.8.1 Internal Oscillator
        2. 9.4.8.2 External Clock
        3. 9.4.8.3 Crystal Oscillator
      9. 9.4.9  Calibration
        1. 9.4.9.1 Offset and Full-Scale Calibration
          1. 9.4.9.1.1 Offset Calibration Registers
          2. 9.4.9.1.2 Full-Scale Calibration Registers
        2. 9.4.9.2 ADC1 Offset Self-Calibration (SFOCAL1)
        3. 9.4.9.3 ADC1 Offset System Calibration (SYOCAL1)
        4. 9.4.9.4 ADC2 Offset Self-Calibration ADC2 (SFOCAL2)
        5. 9.4.9.5 ADC2 Offset System Calibration ADC2 (SYOCAL2)
        6. 9.4.9.6 ADC1 Full-Scale System Calibration (SYGCAL1)
        7. 9.4.9.7 ADC2 Full-Scale System Calibration ADC2 (SYGCAL2)
        8. 9.4.9.8 Calibration Command Procedure
        9. 9.4.9.9 User Calibration Procedure
      10. 9.4.10 Reset
        1. 9.4.10.1 Power-On Reset (POR)
        2. 9.4.10.2 RESET/PWDN Pin
        3. 9.4.10.3 Reset by Command
      11. 9.4.11 Power-Down Mode
      12. 9.4.12 Chop Mode
    5. 9.5 Programming
      1. 9.5.1 NOP Command
      2. 9.5.2 RESET Command
      3. 9.5.3 START1, STOP1, START2, STOP2 Commands
      4. 9.5.4 RDATA1, RDATA2 Commands
      5. 9.5.5 SYOCAL1, SYGCAL1, SFOCAL1, SYOCAL2, SYGCAL2, SFOCAL2 Commands
      6. 9.5.6 RREG Command
      7. 9.5.7 WREG Command
    6. 9.6 Register Maps
      1. 9.6.1  Device Identification Register (address = 00h) [reset = x]
      2. 9.6.2  Power Register (address = 01h) [reset = 11h]
      3. 9.6.3  Interface Register (address = 02h) [reset = 05h]
      4. 9.6.4  Mode0 Register (address = 03h) [reset = 00h]
      5. 9.6.5  Mode1 Register (address = 04h) [reset = 80h]
      6. 9.6.6  Mode2 Register (address = 05h) [reset = 04h]
      7. 9.6.7  Input Multiplexer Register (address = 06h) [reset = 01h]
      8. 9.6.8  Offset Calibration Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
      9. 9.6.9  Full-Scale Calibration Registers (address = 0Ah, 0Bh, 0Ch) [reset = 40h, 00h, 00h]
      10. 9.6.10 IDACMUX Register (address = 0Dh) [reset = BBh]
      11. 9.6.11 IDACMAG Register (address = 0Eh) [reset = 00h]
      12. 9.6.12 REFMUX Register (address = 0Fh) [reset = 00h]
      13. 9.6.13 TDACP Control Register (address = 10h) [reset = 00h]
      14. 9.6.14 TDACN Control Register (address = 11h) [reset = 00h]
      15. 9.6.15 GPIO Connection Register (address = 12h) [reset = 00h]
      16. 9.6.16 GPIO Direction Register (address = 13h) [reset = 00h]
      17. 9.6.17 GPIO Data Register (address = 14h) [reset = 00h]
      18. 9.6.18 ADC2 Configuration Register (address = 15h) [reset = 00h]
      19. 9.6.19 ADC2 Input Multiplexer Register (address = 16h) [reset = 01h]
      20. 9.6.20 ADC2 Offset Calibration Registers (address = 17h, 18h) [reset = 00h, 00h]
      21. 9.6.21 ADC2 Full-Scale Calibration Registers (address = 19h, 1Ah) [reset = 00h, 40h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Isolated (or Floated) Inputs
      2. 10.1.2 Single-Ended Measurements
      3. 10.1.3 Differential Measurements
      4. 10.1.4 Input Range
      5. 10.1.5 Input Filtering
        1. 10.1.5.1 Aliasing
      6. 10.1.6 Input Overload
      7. 10.1.7 Unused Inputs and Outputs
      8. 10.1.8 Voltage Reference
      9. 10.1.9 Serial Interface Connections
    2. 10.2 Typical Application
      1. 10.2.1 3-Wire RTD Measurement with Lead-Wire Compensation
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
    3. 10.3 What To Do and What Not To Do
    4. 10.4 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.1.2 Detailed Design Procedure

The key considerations In the design of a 3-wire RTD circuit are the accuracy, the lead wire compensation, and the sensor self-heating. As the design values of Table 10-2 illustrate, several values of excitation currents are available. The resolution is expressed in units of noise-free bits (NFR). Noise-free resolution is resolution with no code flicker. The selection of excitation currents trades off resolution against sensor self-heating. In general, measurement resolution improves with increasing excitation current. Increasing the excitation current beyond 1000 µA results in no further improvement in resolution. The design procedure is based on 500-µA excitation current, because this level of current results in very low sensor self-heating (0.4 mW).

Table 10-2 RTD Circuit Design Parameters
IIDAC (µA)NFR (bits)PRTD (mW)VRTD(1)
(V)		Gain(2)
(V/V)		VREFMIN(3)
(V)		VREF(4)
(V)		RREF(5)
(kΩ)		VINNLIM(6)
(V)		VINPLIM(7)
(V)		RBIAS(8)
(kΩ)		VRTDN(9)
(V)		VRTDP(10)
(V)		VIDAC1(11)
(V)
5016.80.0010.02320.640.90180.64.17.100.70.71.9
10017.80.0040.04321.281.4114.10.93.85.101.01.12.8
25018.80.0250.10161.601.767.041.13.72.301.21.33.3
50019.10.1000.2081.601.763.521.03.81.101.11.33.4
75018.90.2250.3041.201.321.760.84.00.570.91.22.8
100019.30.4000.4041.601.761.760.93.90.501.01.43.5
150019.10.9000.6021.201.320.880.64.20.230.71.33.0
200018.31.6000.8010.800..900.450.34.50.100.41.22.4
(1) VRTD is the RTD input voltage.
(2) Gain is the ADC gain
(3) VREFMIN is the minimum reference voltage required by the design.
(4) VREF is the design target reference voltage allowing for 10 % over-range or the minimum 0.9 V reference voltage requirement.
(5) RREF is the resistor that senses the IDAC current to generate VREF.
(6) VINNLIM is the absolute minimum input voltage required by the ADC.
(7) VINPLIM is the absolute maximum input voltage required by the ADC.
(8) RBIAS establishes the level-shift voltage.
(9) VRTDN is the design target negative input voltage.
(10) VRTDP is the design target positive input voltage.
(11) VIDAC1 is the design target IDAC1 loop voltage.

Initially, RLEAD1 and RLEAD2 are considered to be 0 Ω. Route the IDAC1 current through the external reference resistor, RREF. IDAC1 generates the ADC reference voltage, VREF, across the reference resistor. This voltage is defined by Equation 24:

Equation 24. VREF = IIDAC1 · RREF

Route the second current (IDAC2) to the second RTD lead.

Program both IDAC1 and IDAC2 to the same value by using the IDACMAG register; however, only the IDAC1 current flows through the reference resistor and RTD. The IDAC1 current excites the RTD to produce a voltage proportional to the RTD resistance. The RTD voltage is defined by Equation 25:

Equation 25. VRTD = RRTD · IIDAC1

The ADC amplifies the RTD signal voltage (VRTD) and measures the resulting voltage against the reference voltage to produce a proportional digital output code, as shown in Equation 26 through Equation 28.

Equation 26. Code ∝ VRTD · Gain / VREF
Equation 27. Code ∝ (RRTD · IIDAC1) · Gain / (IIDAC1 · RREF)
Equation 28. Code ∝ (RRTD · Gain) / RREF

As shown in Equation 28, the RTD measurement depends on the value of the RTD, the PGA gain, and the reference resistor RREF, but not on the IDAC1 value. Therefore, the absolute accuracy and temperature drift of the excitation current does not matter.

The second excitation current (IDAC2) provides a second voltage drop across the second RTD lead resistance, RLEAD2. The second voltage drop compensates the voltage drop caused by IDAC1 and RLEAD1. The leads of a 3-wire RTD typically have the same length; therefore, the lead resistance is typically identical. Taking the lead resistance into account (RLEADx ≠ 0), the differential voltage (VIN) across ADC inputs AIN4 and AIN5 is shown in Equation 29:

Equation 29. VIN = IIDAC1 · (RRTD + RLEAD1) – IIDAC2 · RLEAD2

If RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2, the expression for VIN reduces to Equation 30:

Equation 30. VIN = IIDAC1 · RRTD

In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is compensated, as long as the lead resistance values and the IDAC values are matched.

Using Equation 25, the value of RTD resistance (400 Ω, maximum) and the excitation current (500 μA) yields an RTD voltage of VRTD = 500 μA · 400 Ω = 0.2 V. Use the maximum gain of 8 V/V in order to limit the reference voltage requirement as well as the corresponding loop voltage of IDAC1. The total loop voltage must not exceed the maximum IDAC voltage compliance specification. Gain = 8 requires a minimum reference voltage VREFMIN = 0.2 V · 8 = 1.6 V. To provide a margin for the ADC operating range, increase the target reference voltage by 10% (VREF = 1.6 V · 1.1 = 1.76 V). Calculate the value of the reference resistor, as shown in Equation 31:

Equation 31. RREF = VREF / IIDAC1 = 1.76 V / 500 μA = 3.52 kΩ

For best results, use a precision reference resistor RREF with a low temperature drift (< 10 ppm/°C).

The next step in the design is determining the value of the RBIAS resistor, in order to level shift the RTD voltage to meet the ADC absolute input-voltage specification. The required level-shift voltage is determined by calculating the minimum absolute voltage (VINNLIM) as shown in Equation 32:

Equation 32. VAVSS + 0.3 + VRTD · (Gain – 1) / 2 ≤ VINNLIM

where

  • VRTD = maximum differential RTD voltage = 0.2 V
  • Gain = 8
  • VAVSS = 0 V

The result of the equation requires a minimum absolute input voltage (VRTDN) > 1.0 V. Therefore, the RTD voltage must be level shifted a minimum of 1.0 V. To meet this requirement, a target level-shift value of 1.1 V is chosen to provide 0.1 V margin. Calculate the value of RBIAS as shown in Equation 33:

Equation 33. RBIAS= VINN / (IIDAC1+ IIDAC2) = 1.1 V / ( 2 · 500 μA) = 1.1 kΩ.

After the level-shift voltage is determined, verify that the positive RTD voltage (VRTDP) is less than the maximum absolute input voltage (VINPLIM), as shown in Equation 34:

Equation 34. VINPLIM ≤ VAVDD – 0.3 – VRTD · (Gain – 1) / 2

where

  • VRTD = maximum differential RTD voltage = 0.2 V
  • Gain = 8
  • VAVDD = 4.75 V (minimum)

Solving Equation 34 results in a required VRTDP of less than 3.8 V. Calculate the VRTDP input voltage by Equation 35:

Equation 35. VINP = VRTDN + IIDAC1 · ( RRTD + RLEAD1) = 1.1 V + 500 μA · (400 Ω + 10 Ω) = 1.3 V

Because 1.3 V is less than the 3.8-V maximum input voltage limit, the absolute positive and negative RTD voltages are within the ADC specified input range.

The next step in the design is to verify that the loop voltage of the excitation current is less than the specified IDAC compliance voltage. The IDAC compliance voltage is the maximum voltage drop developed across each IDAC current path to AVSS. In this circuit, IDAC1 has the largest voltage drop developed across its current path. The IDAC1 calculation is sufficient to satisfy IDAC2 because the IDAC2 voltage drop is always less than IDAC1 voltage drop. The sum of voltages in the IDAC1 loop is shown in Equation 36:

Equation 36. VIDAC1 = [(IIDAC1 + IIDAC2) · (RLEAD3 + RBIAS)] + [IIDAC1 · (RRTD + RLEAD1 + RREF)] + VD

where

  • VD = external blocking diode voltage.

The equation results in a loop voltage of VIDAC1= 3.4 V. The worst-case current source compliance voltage is: (VAVDD – 1.1 V) = (4.75 V – 1.1 V) = 3.64 V. The VIDAC1 loop voltage is less than the specified current source compliance voltage (3.4 V < 3.64 V).

Many applications benefit from using an analog filter at the inputs to remove noise and interference from the signal. Filter components are placed on the ADC inputs (RF1, RF2, CDIF1, CCM1, and CCM2), as well as on the reference inputs (RF3, RF4, CDIF2, CCM3, and CCM4). The filters remove both differential and common-mode noise. The application shows a differential input noise filter formed by RF1, RF2 and CDIF, with additional differential mode capacitance provided by the common-mode filter capacitors, CM1 and CM2. Calculate the differential cutoff frequency as shown in Equation 37:

Equation 37. fDIF = 1 / [2π · (RF1 + RF2) · (CDIF1 + CM1|| CM2)]

The common-mode noise filter is formed by components RF1, RF2, CM1 and CM2. Calculate the common-mode signal cutoff frequency as shown in Equation 38:

Equation 38. fCM = 1 / (2π · RF1 · CM1) = 1 / (2π · RF2 · CM2)

Mismatches in the common-mode filter components convert common-mode noise into differential noise. To reduce the effect of mismatch, use a differential mode filter with a corner frequency that is 10 times lower than the common-mode filter corner frequency. The low-frequency differential filter removes the common-mode converted noise. The filter resistors (RFx) also serve as current-limiting resistors. These resistors limit the current into the analog inputs (AINx) of the device to safe levels when an overvoltage occurs on the inputs.

Filter resistors lead to an offset voltage error due to the dc input current leakage flowing into and out of the device. Remove this voltage error by system offset calibration. Resistor values that are too large generate excess thermal noise and degrade the overall noise performance. The recommended range of the filter resistor values is 2 kΩ to 10 kΩ. The properties of the capacitors are important because the capacitors are connected to the signal; use high-quality C0G ceramics or film-type capacitors.

For consistent noise performance across the full range of RTD measurements, match the corner frequencies of the input and reference filter. Detailed information on matching the input and reference filter is found in the RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 application report.